Low-complexity, full-resolution, mirror-switching digital predistortion scheme for polar-modulated power amplifiers

W. H. Yu; W. F. Cheng; Yangmin Li; C. F. Cheang; P. I. Mak; R. P. Martins

doi:10.1049/el.2012.2073

Low-complexity, full-resolution, mirror-switching digital predistortion scheme for polar-modulated power amplifiers

W. H. Yu, W. F. Cheng, Yangmin Li, C. F. Cheang, P. I. Mak, R. P. Martins

Research output: Journal article publication › Journal article › Academic research › peer-review

1 Citation (Scopus)

Abstract

Proposed is a mirror-switching digital predistortion (DPD) scheme with low complexity and full resolution, tailored for power-efficient polar-modulated power amplifiers with nonlinear AM-AM and AM-PM characteristics. The involved digital circuitry is composed of just one CORDIC operator and two 1D look-up tables, avoiding any real-time interpolation or analogue operation. The DPD scheme is verified on a FPGA and the estimated power using a 65nm CMOS technology is 5.2mW. The training time is ∼82s at a clock rate of 100MHz. System-level simulations in MATLAB show significant improvements of error vector magnitude from 104.8 to 2%, and adjacent channel leakage ratio from 21.36 to 49.27dB, under a 20MHz-bandwidth 64-QAM OFDM test signal.

Original language	English
Pages (from-to)	1551-1553
Number of pages	3
Journal	Electronics Letters
Volume	48
Issue number	24
DOIs	https://doi.org/10.1049/el.2012.2073
Publication status	Published - 22 Nov 2012
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el.2012.2073

Cite this

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abstract = "Proposed is a mirror-switching digital predistortion (DPD) scheme with low complexity and full resolution, tailored for power-efficient polar-modulated power amplifiers with nonlinear AM-AM and AM-PM characteristics. The involved digital circuitry is composed of just one CORDIC operator and two 1D look-up tables, avoiding any real-time interpolation or analogue operation. The DPD scheme is verified on a FPGA and the estimated power using a 65nm CMOS technology is 5.2mW. The training time is ∼82s at a clock rate of 100MHz. System-level simulations in MATLAB show significant improvements of error vector magnitude from 104.8 to 2%, and adjacent channel leakage ratio from 21.36 to 49.27dB, under a 20MHz-bandwidth 64-QAM OFDM test signal.",

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AU - Yu, W. H.

AU - Cheng, W. F.

AU - Li, Yangmin

AU - Cheang, C. F.

AU - Mak, P. I.

AU - Martins, R. P.

PY - 2012/11/22

Y1 - 2012/11/22

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DO - 10.1049/el.2012.2073

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Low-complexity, full-resolution, mirror-switching digital predistortion scheme for polar-modulated power amplifiers

Abstract

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