Proposed is a mirror-switching digital predistortion (DPD) scheme with low complexity and full resolution, tailored for power-efficient polar-modulated power amplifiers with nonlinear AM-AM and AM-PM characteristics. The involved digital circuitry is composed of just one CORDIC operator and two 1D look-up tables, avoiding any real-time interpolation or analogue operation. The DPD scheme is verified on a FPGA and the estimated power using a 65nm CMOS technology is 5.2mW. The training time is ∼82s at a clock rate of 100MHz. System-level simulations in MATLAB show significant improvements of error vector magnitude from 104.8 to 2%, and adjacent channel leakage ratio from 21.36 to 49.27dB, under a 20MHz-bandwidth 64-QAM OFDM test signal.
ASJC Scopus subject areas
- Electrical and Electronic Engineering