Loop scheduling with memory access reduction under register constraints for DSP applications

Meng Wang, Duo Liu, Yi Wang, Zili Shao

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

1 Citation (Scopus)

Abstract

In embedded systems, high-performance DSP needs to be performed not only with high-data throughput but also with low-power consumption. In this paper, we propose an effective scheduling framework, MARLS (Memory Access Reduction Loop Scheduling), to reduce memory accesses for DSP applications with loops. In the framework, we generate register operations to replace redundant load operations, and schedule these operations while allocating available physical registers to their register operands. We implement our technique into the Trimaran compiler and conduct experiments using a set of benchmarks from DSPstone and MiBench on the cycle-accurate VLIW simulator of Trimaran. The experimental results show that our technique significantly reduces the number of memory accesses.
Original languageEnglish
Title of host publication2009 IEEE Workshop on Signal Processing Systems, SiPS 2009 - Proceedings
Pages139-144
Number of pages6
DOIs
Publication statusPublished - 1 Dec 2009
Event2009 IEEE Workshop on Signal Processing Systems, SiPS 2009 - Tampere, Finland
Duration: 7 Oct 20099 Oct 2009

Conference

Conference2009 IEEE Workshop on Signal Processing Systems, SiPS 2009
CountryFinland
CityTampere
Period7/10/099/10/09

Keywords

  • Memory management
  • Processor scheduling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture

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