Abstract
Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP) applications. It is important to study effective and efficient transformation techniques to increase parallelism for nested loops. In this paper, we propose a novel technique, iterational retiming, that can satisfy any given timing constraint by achieving full parallelism for iterations in a partition. Theorems and efficient algorithms are proposed for iterational retiming. The experimental results show that iterational retiming is a promising technique for parallel embedded systems. It can achieve 87% improvement over software pipelining and 88% improvement over loop unfolding on average.
Original language | English |
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Title of host publication | CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and Systems Synthesis |
Pages | 309-314 |
Number of pages | 6 |
Publication status | Published - 11 Nov 2005 |
Externally published | Yes |
Event | 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis CODES+ISSS 2005 - Jersey City, NJ, United States Duration: 18 Sept 2005 → 21 Sept 2005 |
Conference
Conference | 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis CODES+ISSS 2005 |
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Country/Territory | United States |
City | Jersey City, NJ |
Period | 18/09/05 → 21/09/05 |
Keywords
- Nested Loops
- Optimization
- Partition
- Retiming
ASJC Scopus subject areas
- General Engineering