Investigation of the source/drain asymmetric effects due to gate misalignment in planar double-gate MOSFETs

Chunshan Yin, Philip Ching Ho Chan

Research output: Journal article publicationJournal articleAcademic researchpeer-review

36 Citations (Scopus)


A planar double-gate SOI MOSFET (DG-SOI) with thin channel and thick source/drain (S/D) was successfully fabricated. Using both experimental data and simulation results, the S/D asymmetric effect induced by gate misalignment was studied. For a misaligned DG-SOI, there is gate nonoverlapped region on one side and extra gate overlapped region on the other side. The nonoverlapped region introduces extra series resistance and weakly controlled channel, while the extra overlapped region introduces additional overlap capacitance and gate leakage current. We compared two cases: bottom gate shift to source side (DG_S) and bottom gate shift to drain side (DG_D). At the same gate misalignment value, DG_S resulted in a larger drain-induced barrier lowering effect and smaller overlap capacitance at drain side than DG_D. Because of reduced drain-side capacitance, the speed of three-stage ring oscillator of DG_S, with 20% gate misalignment length (Lmis) over gate length (Lg), or Lmis/Lg= 20%, was faster than that of two-gate aligned DG-SOI.
Original languageEnglish
Pages (from-to)85-90
Number of pages6
JournalIEEE Transactions on Electron Devices
Issue number1
Publication statusPublished - 1 Jan 2005
Externally publishedYes


  • Double-gate (DG)
  • Gate misalignment
  • Gate-all-around transistor (GAT)
  • Silicon-on-insulator (SOI)
  • Source/drain asymmetry

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)


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