Investigation and optimization of pin multiplexing in high-Level synthesis

Shuangnan Liu, Francis Lau, Benjamin Carrion Schafer

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

2 Citations (Scopus)

Abstract

This paper investigates the effect of pin multiplexing on the resultant micro-architecture of synthesizable behavioral descriptions for High-Level Synthesis (HLS). A method is presented to find the most efficient pin assignments by assigning multiple logic inputs and outputs to the same physical ports such that the performance degradation and area overhead is minimized. The proposed method is a fast heuristic based on the scheduling results of HLS seen as a black box and hence is flexible enough to work with any HLS tool. Experimental results show that our proposed method is very efficient compared to an exhaustive search and a simulated annealing method at a fraction of the time and much better than randomly selecting the pins to be multiplexed.

Original languageEnglish
Title of host publicationGLSVLSI 2018 - Proceedings of the 2018 Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery
Pages427-430
Number of pages4
ISBN (Electronic)9781450357241
DOIs
Publication statusPublished - 23 May 2018
Event28th Great Lakes Symposium on VLSI, GLSVLSI 2018 - Chicago, United States
Duration: 23 May 201825 May 2018

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference28th Great Lakes Symposium on VLSI, GLSVLSI 2018
CountryUnited States
CityChicago
Period23/05/1825/05/18

Keywords

  • High-level synthesis
  • IOs
  • Micro-architecture
  • Pin multiplexing

ASJC Scopus subject areas

  • Engineering(all)

Cite this