Improved strategy with transistor re-sizing capability for converting bulk CMOS polygon layout to SOI

Mike C.W. Chow; Philip Ching Ho Chan

Improved strategy with transistor re-sizing capability for converting bulk CMOS polygon layout to SOI

Mike C.W. Chow, Philip Ching Ho Chan

Research output: Journal article publication › Conference article › Academic research › peer-review

Abstract

The SOI (Silicon On Insulator) CMOS has many potential advantages over the traditional bulk CMOS circuit as it is free of latch-up and has improved performance and higher packing density [1, 2]. With the recent advances in high-quality thin-film SOI wafer technology, it is becoming a viable technology for ULSI. As SOI emerges as an alternate to bulk CMOS for low power and high-speed applications, an automated methodology will expedite the conversion of existing bulk CMOS designs to SOI CMOS.

Original language	English
Pages (from-to)	767-770
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	4
Publication status	Published - 1 Jan 1996
Externally published	Yes
Event	Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, United States Duration: 12 May 1996 → 15 May 1996

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

@article{398b72496c754a6082fc4bb76be50286,

title = "Improved strategy with transistor re-sizing capability for converting bulk CMOS polygon layout to SOI",

abstract = "The SOI (Silicon On Insulator) CMOS has many potential advantages over the traditional bulk CMOS circuit as it is free of latch-up and has improved performance and higher packing density [1, 2]. With the recent advances in high-quality thin-film SOI wafer technology, it is becoming a viable technology for ULSI. As SOI emerges as an alternate to bulk CMOS for low power and high-speed applications, an automated methodology will expedite the conversion of existing bulk CMOS designs to SOI CMOS.",

author = "Chow, \{Mike C.W.\} and Chan, \{Philip Ching Ho\}",

year = "1996",

month = jan,

day = "1",

language = "English",

volume = "4",

pages = "767--770",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "IEEE",

note = "Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) ; Conference date: 12-05-1996 Through 15-05-1996",

}

TY - JOUR

T1 - Improved strategy with transistor re-sizing capability for converting bulk CMOS polygon layout to SOI

AU - Chow, Mike C.W.

AU - Chan, Philip Ching Ho

PY - 1996/1/1

Y1 - 1996/1/1

N2 - The SOI (Silicon On Insulator) CMOS has many potential advantages over the traditional bulk CMOS circuit as it is free of latch-up and has improved performance and higher packing density [1, 2]. With the recent advances in high-quality thin-film SOI wafer technology, it is becoming a viable technology for ULSI. As SOI emerges as an alternate to bulk CMOS for low power and high-speed applications, an automated methodology will expedite the conversion of existing bulk CMOS designs to SOI CMOS.

AB - The SOI (Silicon On Insulator) CMOS has many potential advantages over the traditional bulk CMOS circuit as it is free of latch-up and has improved performance and higher packing density [1, 2]. With the recent advances in high-quality thin-film SOI wafer technology, it is becoming a viable technology for ULSI. As SOI emerges as an alternate to bulk CMOS for low power and high-speed applications, an automated methodology will expedite the conversion of existing bulk CMOS designs to SOI CMOS.

UR - https://www.scopus.com/pages/publications/0029708324

M3 - Conference article

SN - 0271-4310

VL - 4

SP - 767

EP - 770

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4)

Y2 - 12 May 1996 through 15 May 1996

ER -

Improved strategy with transistor re-sizing capability for converting bulk CMOS polygon layout to SOI

Abstract

ASJC Scopus subject areas

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