Improved strategy with transistor re-sizing capability for converting bulk CMOS polygon layout to SOI

Mike C.W. Chow, Philip Ching Ho Chan

Research output: Journal article publicationConference articleAcademic researchpeer-review

Abstract

The SOI (Silicon On Insulator) CMOS has many potential advantages over the traditional bulk CMOS circuit as it is free of latch-up and has improved performance and higher packing density [1, 2]. With the recent advances in high-quality thin-film SOI wafer technology, it is becoming a viable technology for ULSI. As SOI emerges as an alternate to bulk CMOS for low power and high-speed applications, an automated methodology will expedite the conversion of existing bulk CMOS designs to SOI CMOS.
Original languageEnglish
Pages (from-to)767-770
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
Publication statusPublished - 1 Jan 1996
Externally publishedYes
EventProceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, United States
Duration: 12 May 199615 May 1996

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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