Abstract
Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), are very popular in today's embedded systems design due to their low-cost, high-performance and flexibility. Partially Runtime-Reconfigurable (PRTR) FPGAs allow hardware tasks to be placed and removed dynamically at runtime. Hardware task scheduling on PRTR FPGAs brings many challenging issues to traditional real-time scheduling theory, which have not been adequately addressed by the research community compared to software task scheduling on CPUs. In this paper, we consider the schedulability analysis problem of HW task scheduling on PRPR FPGAs. We derive utilization bound tests for two variants of global EDF scheduling, and use synthetic tasksets to compare performance of the tests to existing work and simulation results.
Original language | English |
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Title of host publication | Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM |
DOIs | |
Publication status | Published - 24 Sept 2007 |
Externally published | Yes |
Event | 21st International Parallel and Distributed Processing Symposium, IPDPS 2007 - Long Beach, CA, United States Duration: 26 Mar 2007 → 30 Mar 2007 |
Conference
Conference | 21st International Parallel and Distributed Processing Symposium, IPDPS 2007 |
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Country/Territory | United States |
City | Long Beach, CA |
Period | 26/03/07 → 30/03/07 |
ASJC Scopus subject areas
- Hardware and Architecture
- Software
- General Mathematics