Improved schedulability analysis of EDF scheduling on reconfigurable hardware devices

Nan Guan, Zonghua Gu, Qingxu Deng, Weichen Liu, Ge Yu

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

4 Citations (Scopus)


Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), are very popular in today's embedded systems design due to their low-cost, high-performance and flexibility. Partially Runtime-Reconfigurable (PRTR) FPGAs allow hardware tasks to be placed and removed dynamically at runtime. Hardware task scheduling on PRTR FPGAs brings many challenging issues to traditional real-time scheduling theory, which have not been adequately addressed by the research community compared to software task scheduling on CPUs. In this paper, we consider the schedulability analysis problem of HW task scheduling on PRPR FPGAs. We derive utilization bound tests for two variants of global EDF scheduling, and use synthetic tasksets to compare performance of the tests to existing work and simulation results.
Original languageEnglish
Title of host publicationProceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM
Publication statusPublished - 24 Sep 2007
Externally publishedYes
Event21st International Parallel and Distributed Processing Symposium, IPDPS 2007 - Long Beach, CA, United States
Duration: 26 Mar 200730 Mar 2007


Conference21st International Parallel and Distributed Processing Symposium, IPDPS 2007
Country/TerritoryUnited States
CityLong Beach, CA

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Mathematics(all)

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