I-cache tag reduction for low power chip multiprocessor

Long Zheng, Mianxiong Dong, Song Guo, Minyi Guo, Li Li

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

2 Citations (Scopus)

Abstract

Energy consumption is a major consideration in microprocessor optimization. This paper presents a tagreduction based approach for energy saving in L1 I-Cache (instruction cache) of Chip Multiprocessors (CMP). To our best knowledge, this is the first work that extends the tag reduction technique to the CMP. We formulate our approach to an equivalent problem which is to find an assignment of the whole instruction pages in the physical memory to a set of cores such that the tag-reduction conflicts for each core can be mostly avoided or reduced. We then propose three algorithms using different heuristics for this assignment problem. The experimental results show that our proposed algorithms can save the total power up to 45.33% in average compared to the one that the tag-reduction is not used. They outperform significantly the tag-reduction based algorithm on single-core processor as well.
Original languageEnglish
Title of host publicationProceedings - 2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009
Pages196-202
Number of pages7
DOIs
Publication statusPublished - 19 Nov 2009
Externally publishedYes
Event2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009 - Chengdu, Sichuan, China
Duration: 9 Aug 200912 Aug 2009

Conference

Conference2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009
Country/TerritoryChina
CityChengdu, Sichuan
Period9/08/0912/08/09

Keywords

  • Chip multiprocessor
  • Energy saving
  • Tag reduction

ASJC Scopus subject areas

  • Computer Science Applications
  • Software

Cite this