Hybrid reconfigurable architecture for low power digital signal processing system

Chun Hok Ho, Ka Fai Cedric Yiu

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

1 Citation (Scopus)

Abstract

This paper presents an architecture for a hybrid re-configurable device which is specifically optimized for acoustic applications. In the proposed architecture, Finegrained units are used for implementing control logic and bit-oriented operations, while parameterised and reconfigurable word-based coarse-grained units incorporating word-oriented lookup tables and fast fourier transformation (FFT) are used to implement datapaths. In order to facilitate comparison with existing FPGA devices, the virtual embedded block (WEB) scheme is proposed to model embedded blocks using existing FPGA tools. This methodology involves adopting existing FPGA resources to model the size, position and delay of the embedded elements. We show significant power reduction when comparing with existing reconfigurable device implementing the same acoustic applications.
Original languageEnglish
Title of host publication1st International Conference on Green Circuits and Systems, ICGCS 2010
Pages370-374
Number of pages5
DOIs
Publication statusPublished - 20 Sep 2010
Event1st International Conference on Green Circuits and Systems, ICGCS 2010 - Shanghai, China
Duration: 21 Jun 201023 Jun 2010

Conference

Conference1st International Conference on Green Circuits and Systems, ICGCS 2010
Country/TerritoryChina
CityShanghai
Period21/06/1023/06/10

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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