We demonstrate a 2-transistor/2-resistor (2T2R) static-random-access-memory (SRAM) cell with high read/write stability composed of two-surface-channel (TSC) transistors, using two-dimensional (2D) layered MoS2. The 2T2R SRAM cell consists of fewer transistors than a conventional 6-transistor (6T) SRAM cell by fully utilizing high-area-efficiency structure of TSC MoS2 transistors. We verify the channel material thickness-dependent logic behavior between AND and OR. Simultaneously, the 2T2R SRAM exhibits stable read and write operations with a 32.6 % read normalized noise margin (NM) and a 50.2 % write normalized NM under optimal resistance and supply voltage conditions. The read and write power of the memory devices are 0.035 μW and 0.036 μW, respectively, indicating a promising application in low-power electronics and highly area-efficient chips.