Highly Area-Efficient Low-Power SRAM Cell with 2 Transistors and 2 Resistors

Jiayi Li; Peng Zhou; Jingyu Li; Yi DIng; Chunsen Liu; Xiang Hou; Huawei Chen; Yan Xiong; David Wei Zhang; Yang Chai

doi:10.1109/IEDM19573.2019.8993520

Highly Area-Efficient Low-Power SRAM Cell with 2 Transistors and 2 Resistors

Jiayi Li, Peng Zhou, Jingyu Li, Yi DIng, Chunsen Liu, Xiang Hou, Huawei Chen, Yan Xiong, David Wei Zhang, Yang Chai

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

10 Citations (Scopus)

Abstract

We demonstrate a 2-transistor/2-resistor (2T2R) static-random-access-memory (SRAM) cell with high read/write stability composed of two-surface-channel (TSC) transistors, using two-dimensional (2D) layered MoS₂. The 2T2R SRAM cell consists of fewer transistors than a conventional 6-transistor (6T) SRAM cell by fully utilizing high-area-efficiency structure of TSC MoS₂ transistors. We verify the channel material thickness-dependent logic behavior between AND and OR. Simultaneously, the 2T2R SRAM exhibits stable read and write operations with a 32.6 % read normalized noise margin (NM) and a 50.2 % write normalized NM under optimal resistance and supply voltage conditions. The read and write power of the memory devices are 0.035 μW and 0.036 μW, respectively, indicating a promising application in low-power electronics and highly area-efficient chips.

Original language	English
Title of host publication	2019 IEEE International Electron Devices Meeting, IEDM 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728140315
DOIs	https://doi.org/10.1109/IEDM19573.2019.8993520
Publication status	Published - Dec 2019
Event	65th Annual IEEE International Electron Devices Meeting, IEDM 2019 - San Francisco, United States Duration: 7 Dec 2019 → 11 Dec 2019

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2019-December
ISSN (Print)	0163-1918

Conference

Conference	65th Annual IEEE International Electron Devices Meeting, IEDM 2019
Country/Territory	United States
City	San Francisco
Period	7/12/19 → 11/12/19

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

More information

10.1109/IEDM19573.2019.8993520

Cite this

Li, J., Zhou, P., Li, J., DIng, Y., Liu, C., Hou, X., Chen, H., Xiong, Y., Zhang, D. W., & Chai, Y. (2019). Highly Area-Efficient Low-Power SRAM Cell with 2 Transistors and 2 Resistors. In 2019 IEEE International Electron Devices Meeting, IEDM 2019 Article 8993520 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2019-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM19573.2019.8993520

@inproceedings{143d810614cd4b3f990ce1447d1e20ba,

title = "Highly Area-Efficient Low-Power SRAM Cell with 2 Transistors and 2 Resistors",

abstract = "We demonstrate a 2-transistor/2-resistor (2T2R) static-random-access-memory (SRAM) cell with high read/write stability composed of two-surface-channel (TSC) transistors, using two-dimensional (2D) layered MoS2. The 2T2R SRAM cell consists of fewer transistors than a conventional 6-transistor (6T) SRAM cell by fully utilizing high-area-efficiency structure of TSC MoS2 transistors. We verify the channel material thickness-dependent logic behavior between AND and OR. Simultaneously, the 2T2R SRAM exhibits stable read and write operations with a 32.6 % read normalized noise margin (NM) and a 50.2 % write normalized NM under optimal resistance and supply voltage conditions. The read and write power of the memory devices are 0.035 μW and 0.036 μW, respectively, indicating a promising application in low-power electronics and highly area-efficient chips.",

author = "Jiayi Li and Peng Zhou and Jingyu Li and Yi DIng and Chunsen Liu and Xiang Hou and Huawei Chen and Yan Xiong and Zhang, {David Wei} and Yang Chai",

year = "2019",

month = dec,

doi = "10.1109/IEDM19573.2019.8993520",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 IEEE International Electron Devices Meeting, IEDM 2019",

note = "65th Annual IEEE International Electron Devices Meeting, IEDM 2019 ; Conference date: 07-12-2019 Through 11-12-2019",

}

Li, J, Zhou, P, Li, J, DIng, Y, Liu, C, Hou, X, Chen, H, Xiong, Y, Zhang, DW & Chai, Y 2019, Highly Area-Efficient Low-Power SRAM Cell with 2 Transistors and 2 Resistors. in 2019 IEEE International Electron Devices Meeting, IEDM 2019., 8993520, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2019-December, Institute of Electrical and Electronics Engineers Inc., 65th Annual IEEE International Electron Devices Meeting, IEDM 2019, San Francisco, United States, 7/12/19. https://doi.org/10.1109/IEDM19573.2019.8993520

Highly Area-Efficient Low-Power SRAM Cell with 2 Transistors and 2 Resistors. / Li, Jiayi; Zhou, Peng; Li, Jingyu et al.
2019 IEEE International Electron Devices Meeting, IEDM 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8993520 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2019-December).

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

TY - GEN

T1 - Highly Area-Efficient Low-Power SRAM Cell with 2 Transistors and 2 Resistors

AU - Li, Jiayi

AU - Zhou, Peng

AU - Li, Jingyu

AU - DIng, Yi

AU - Liu, Chunsen

AU - Hou, Xiang

AU - Chen, Huawei

AU - Xiong, Yan

AU - Zhang, David Wei

AU - Chai, Yang

PY - 2019/12

Y1 - 2019/12

N2 - We demonstrate a 2-transistor/2-resistor (2T2R) static-random-access-memory (SRAM) cell with high read/write stability composed of two-surface-channel (TSC) transistors, using two-dimensional (2D) layered MoS2. The 2T2R SRAM cell consists of fewer transistors than a conventional 6-transistor (6T) SRAM cell by fully utilizing high-area-efficiency structure of TSC MoS2 transistors. We verify the channel material thickness-dependent logic behavior between AND and OR. Simultaneously, the 2T2R SRAM exhibits stable read and write operations with a 32.6 % read normalized noise margin (NM) and a 50.2 % write normalized NM under optimal resistance and supply voltage conditions. The read and write power of the memory devices are 0.035 μW and 0.036 μW, respectively, indicating a promising application in low-power electronics and highly area-efficient chips.

AB - We demonstrate a 2-transistor/2-resistor (2T2R) static-random-access-memory (SRAM) cell with high read/write stability composed of two-surface-channel (TSC) transistors, using two-dimensional (2D) layered MoS2. The 2T2R SRAM cell consists of fewer transistors than a conventional 6-transistor (6T) SRAM cell by fully utilizing high-area-efficiency structure of TSC MoS2 transistors. We verify the channel material thickness-dependent logic behavior between AND and OR. Simultaneously, the 2T2R SRAM exhibits stable read and write operations with a 32.6 % read normalized noise margin (NM) and a 50.2 % write normalized NM under optimal resistance and supply voltage conditions. The read and write power of the memory devices are 0.035 μW and 0.036 μW, respectively, indicating a promising application in low-power electronics and highly area-efficient chips.

UR - http://www.scopus.com/inward/record.url?scp=85081052962&partnerID=8YFLogxK

U2 - 10.1109/IEDM19573.2019.8993520

DO - 10.1109/IEDM19573.2019.8993520

M3 - Conference article published in proceeding or book

AN - SCOPUS:85081052962

T3 - Technical Digest - International Electron Devices Meeting, IEDM

BT - 2019 IEEE International Electron Devices Meeting, IEDM 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 65th Annual IEEE International Electron Devices Meeting, IEDM 2019

Y2 - 7 December 2019 through 11 December 2019

ER -

Highly Area-Efficient Low-Power SRAM Cell with 2 Transistors and 2 Resistors

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