Highly Area-Efficient Low-Power SRAM Cell with 2 Transistors and 2 Resistors

Jiayi Li, Peng Zhou, Jingyu Li, Yi DIng, Chunsen Liu, Xiang Hou, Huawei Chen, Yan Xiong, David Wei Zhang, Yang Chai

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

3 Citations (Scopus)


We demonstrate a 2-transistor/2-resistor (2T2R) static-random-access-memory (SRAM) cell with high read/write stability composed of two-surface-channel (TSC) transistors, using two-dimensional (2D) layered MoS2. The 2T2R SRAM cell consists of fewer transistors than a conventional 6-transistor (6T) SRAM cell by fully utilizing high-area-efficiency structure of TSC MoS2 transistors. We verify the channel material thickness-dependent logic behavior between AND and OR. Simultaneously, the 2T2R SRAM exhibits stable read and write operations with a 32.6 % read normalized noise margin (NM) and a 50.2 % write normalized NM under optimal resistance and supply voltage conditions. The read and write power of the memory devices are 0.035 μW and 0.036 μW, respectively, indicating a promising application in low-power electronics and highly area-efficient chips.

Original languageEnglish
Title of host publication2019 IEEE International Electron Devices Meeting, IEDM 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728140315
Publication statusPublished - Dec 2019
Event65th Annual IEEE International Electron Devices Meeting, IEDM 2019 - San Francisco, United States
Duration: 7 Dec 201911 Dec 2019

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918


Conference65th Annual IEEE International Electron Devices Meeting, IEDM 2019
Country/TerritoryUnited States
CitySan Francisco

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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