High-Q SOI gated varactor for use in RF ICs

Frankie Hui, Zhiheng Chen, Keqiang Shen, Jack Lau, Magaret Huang, Mansun Chan, Ping K. Ko, Gongjiu Jin, Philip Ching Ho Chan

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

5 Citations (Scopus)


A thin-film silicon-on-insulator (SOI) gated varactor based on a gated pin diode structure achieves a nominal capacitance of 7pF with a sensitivity of 5pF/V through the anode-cathode voltage. A third terminal provides an additional tuning flexibility and offers a 1pF/V sensitivity. S-parameter measurement reveals a Q of 14. The process is done without any modification to an industrial SOI CMOS process. The nominal capacitance can be varied with different gate bias. With the structure of the varactor, a flexibility in the capacitance tuning range, capacitance-voltage slope and Q values can be achieved by choosing either of the complementary devices and the appropriate biasing condition of Vg and Vd upon circuit requirement.
Original languageEnglish
Title of host publicationIEEE International SOI Conference
Number of pages2
Publication statusPublished - 1 Dec 1998
Externally publishedYes
EventProceedings of the 1998 IEEE International SOI Conference - Stuart, FL, United States
Duration: 5 Oct 19988 Oct 1998


ConferenceProceedings of the 1998 IEEE International SOI Conference
Country/TerritoryUnited States
CityStuart, FL

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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