High-Q SOI gated varactor for use in RF ICs

Frankie Hui; Zhiheng Chen; Keqiang Shen; Jack Lau; Magaret Huang; Mansun Chan; Ping K. Ko; Gongjiu Jin; Philip Ching Ho Chan

High-Q SOI gated varactor for use in RF ICs

Frankie Hui, Zhiheng Chen, Keqiang Shen, Jack Lau, Magaret Huang, Mansun Chan, Ping K. Ko, Gongjiu Jin, Philip Ching Ho Chan

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

5 Citations (Scopus)

Abstract

A thin-film silicon-on-insulator (SOI) gated varactor based on a gated pin diode structure achieves a nominal capacitance of 7pF with a sensitivity of 5pF/V through the anode-cathode voltage. A third terminal provides an additional tuning flexibility and offers a 1pF/V sensitivity. S-parameter measurement reveals a Q of 14. The process is done without any modification to an industrial SOI CMOS process. The nominal capacitance can be varied with different gate bias. With the structure of the varactor, a flexibility in the capacitance tuning range, capacitance-voltage slope and Q values can be achieved by choosing either of the complementary devices and the appropriate biasing condition of Vg and Vd upon circuit requirement.

Original language	English
Title of host publication	IEEE International SOI Conference
Publisher	IEEE
Pages	31-32
Number of pages	2
Publication status	Published - 1 Dec 1998
Externally published	Yes
Event	Proceedings of the 1998 IEEE International SOI Conference - Stuart, FL, United States Duration: 5 Oct 1998 → 8 Oct 1998

Conference

Conference	Proceedings of the 1998 IEEE International SOI Conference
Country/Territory	United States
City	Stuart, FL
Period	5/10/98 → 8/10/98

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

@inproceedings{ce13a38407484b488500759724872655,

title = "High-Q SOI gated varactor for use in RF ICs",

abstract = "A thin-film silicon-on-insulator (SOI) gated varactor based on a gated pin diode structure achieves a nominal capacitance of 7pF with a sensitivity of 5pF/V through the anode-cathode voltage. A third terminal provides an additional tuning flexibility and offers a 1pF/V sensitivity. S-parameter measurement reveals a Q of 14. The process is done without any modification to an industrial SOI CMOS process. The nominal capacitance can be varied with different gate bias. With the structure of the varactor, a flexibility in the capacitance tuning range, capacitance-voltage slope and Q values can be achieved by choosing either of the complementary devices and the appropriate biasing condition of Vg and Vd upon circuit requirement.",

author = "Frankie Hui and Zhiheng Chen and Keqiang Shen and Jack Lau and Magaret Huang and Mansun Chan and Ko, {Ping K.} and Gongjiu Jin and Chan, {Philip Ching Ho}",

year = "1998",

month = dec,

day = "1",

language = "English",

pages = "31--32",

booktitle = "IEEE International SOI Conference",

publisher = "IEEE",

address = "United States",

note = "Proceedings of the 1998 IEEE International SOI Conference ; Conference date: 05-10-1998 Through 08-10-1998",

}

TY - GEN

T1 - High-Q SOI gated varactor for use in RF ICs

AU - Hui, Frankie

AU - Chen, Zhiheng

AU - Shen, Keqiang

AU - Lau, Jack

AU - Huang, Magaret

AU - Chan, Mansun

AU - Ko, Ping K.

AU - Jin, Gongjiu

AU - Chan, Philip Ching Ho

PY - 1998/12/1

Y1 - 1998/12/1

N2 - A thin-film silicon-on-insulator (SOI) gated varactor based on a gated pin diode structure achieves a nominal capacitance of 7pF with a sensitivity of 5pF/V through the anode-cathode voltage. A third terminal provides an additional tuning flexibility and offers a 1pF/V sensitivity. S-parameter measurement reveals a Q of 14. The process is done without any modification to an industrial SOI CMOS process. The nominal capacitance can be varied with different gate bias. With the structure of the varactor, a flexibility in the capacitance tuning range, capacitance-voltage slope and Q values can be achieved by choosing either of the complementary devices and the appropriate biasing condition of Vg and Vd upon circuit requirement.

AB - A thin-film silicon-on-insulator (SOI) gated varactor based on a gated pin diode structure achieves a nominal capacitance of 7pF with a sensitivity of 5pF/V through the anode-cathode voltage. A third terminal provides an additional tuning flexibility and offers a 1pF/V sensitivity. S-parameter measurement reveals a Q of 14. The process is done without any modification to an industrial SOI CMOS process. The nominal capacitance can be varied with different gate bias. With the structure of the varactor, a flexibility in the capacitance tuning range, capacitance-voltage slope and Q values can be achieved by choosing either of the complementary devices and the appropriate biasing condition of Vg and Vd upon circuit requirement.

UR - http://www.scopus.com/inward/record.url?scp=0032319067&partnerID=8YFLogxK

M3 - Conference article published in proceeding or book

SP - 31

EP - 32

BT - IEEE International SOI Conference

PB - IEEE

T2 - Proceedings of the 1998 IEEE International SOI Conference

Y2 - 5 October 1998 through 8 October 1998

ER -

High-Q SOI gated varactor for use in RF ICs

Abstract

Conference

ASJC Scopus subject areas

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