High-performance logic and memory devices based on a dual-gated MoS2 architecture

Fuyou Liao; Zhongxun Guo; Yin Wang; Yufeng Xie; Simeng Zhang; Yaochen Sheng; Hongwei Tang; Zihan Xu; Antoine Riaud; Peng Zhou; Jing Wan; Michael S. Fuhrer; Xiangwei Jiang; David Wei Zhang; Yang Chai; Wenzhong Bao

doi:10.1021/acsaelm.9b00628

High-performance logic and memory devices based on a dual-gated MoS₂ architecture

Fuyou Liao, Zhongxun Guo, Yin Wang, Yufeng Xie, Simeng Zhang, Yaochen Sheng, Hongwei Tang, Zihan Xu, Antoine Riaud, Peng Zhou, Jing Wan, Michael S. Fuhrer, Xiangwei Jiang, David Wei Zhang, Yang Chai, Wenzhong Bao

Research output: Journal article publication › Journal article › Academic research › peer-review

30 Citations (Scopus)

Abstract

We demonstrate dual-gated (DG) MoS₂ field effect transistors (FETs) in which the degraded switching performance of multilayer MoS₂ can be compensated by the DG structure. It produces large current density (>100 μA/μm for a monolayer), steep subthreshold swing (SS) (∼100 mV/dec for 5 nm thickness), and high on/off current ratio (>10⁷ for 10 nm thickness). Such DG structure not only improves electrostatic control but also provides an extra degree of freedom for manipulating the threshold voltage (V_TH) and SS by separately tuning the top and back gate voltages, which are demonstrated in a logic inverter. Dynamic random access memory (DRAM) has a short retention time because of large OFF-state current in the Si MOSFET. Based on our DG MoS₂-FETs, a DRAM unit cell with a long retention time of 1260 ms is realized. Large-scale isolated MoS₂ DG-FETs based on CVD-synthesized continuous films are also demonstrated, which show potential applications for future wafer-scale digital and low-power electronics.

Original language	English
Pages (from-to)	111-119
Number of pages	9
Journal	ACS Applied Electronic Materials
Volume	2
Issue number	1
DOIs	https://doi.org/10.1021/acsaelm.9b00628
Publication status	Published - 28 Jan 2020

Keywords

Dual-gate
Dynamic random access memory cells
Field-effect transistors
Inverters
MoS

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Materials Chemistry
Electrochemistry

More information

10.1021/acsaelm.9b00628

Cite this

@article{f3a481c37d7044dc8d3c7304b494b935,

title = "High-performance logic and memory devices based on a dual-gated MoS2 architecture",

abstract = "We demonstrate dual-gated (DG) MoS2 field effect transistors (FETs) in which the degraded switching performance of multilayer MoS2 can be compensated by the DG structure. It produces large current density (>100 μA/μm for a monolayer), steep subthreshold swing (SS) (∼100 mV/dec for 5 nm thickness), and high on/off current ratio (>107 for 10 nm thickness). Such DG structure not only improves electrostatic control but also provides an extra degree of freedom for manipulating the threshold voltage (VTH) and SS by separately tuning the top and back gate voltages, which are demonstrated in a logic inverter. Dynamic random access memory (DRAM) has a short retention time because of large OFF-state current in the Si MOSFET. Based on our DG MoS2-FETs, a DRAM unit cell with a long retention time of 1260 ms is realized. Large-scale isolated MoS2 DG-FETs based on CVD-synthesized continuous films are also demonstrated, which show potential applications for future wafer-scale digital and low-power electronics.",

keywords = "Dual-gate, Dynamic random access memory cells, Field-effect transistors, Inverters, MoS",

author = "Fuyou Liao and Zhongxun Guo and Yin Wang and Yufeng Xie and Simeng Zhang and Yaochen Sheng and Hongwei Tang and Zihan Xu and Antoine Riaud and Peng Zhou and Jing Wan and Fuhrer, {Michael S.} and Xiangwei Jiang and Zhang, {David Wei} and Yang Chai and Wenzhong Bao",

note = "Funding Information: This work was supported by the National Key Research and Development Program of China (2016YFA0203900 and 2018YFA0306101) and the Natural Science Foundation of China (Grant No. 61874154). M.S.F. acknowledges support from the Australian Research Council under Grant DP150103837. Publisher Copyright: {\textcopyright} 2019 American Chemical Society",

year = "2020",

month = jan,

day = "28",

doi = "10.1021/acsaelm.9b00628",

language = "English",

volume = "2",

pages = "111--119",

journal = "ACS Applied Electronic Materials",

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publisher = "American Chemical Society",

number = "1",

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TY - JOUR

T1 - High-performance logic and memory devices based on a dual-gated MoS2 architecture

AU - Liao, Fuyou

AU - Guo, Zhongxun

AU - Wang, Yin

AU - Xie, Yufeng

AU - Zhang, Simeng

AU - Sheng, Yaochen

AU - Tang, Hongwei

AU - Xu, Zihan

AU - Riaud, Antoine

AU - Zhou, Peng

AU - Wan, Jing

AU - Fuhrer, Michael S.

AU - Jiang, Xiangwei

AU - Zhang, David Wei

AU - Chai, Yang

AU - Bao, Wenzhong

N1 - Funding Information: This work was supported by the National Key Research and Development Program of China (2016YFA0203900 and 2018YFA0306101) and the Natural Science Foundation of China (Grant No. 61874154). M.S.F. acknowledges support from the Australian Research Council under Grant DP150103837. Publisher Copyright: © 2019 American Chemical Society

PY - 2020/1/28

Y1 - 2020/1/28

N2 - We demonstrate dual-gated (DG) MoS2 field effect transistors (FETs) in which the degraded switching performance of multilayer MoS2 can be compensated by the DG structure. It produces large current density (>100 μA/μm for a monolayer), steep subthreshold swing (SS) (∼100 mV/dec for 5 nm thickness), and high on/off current ratio (>107 for 10 nm thickness). Such DG structure not only improves electrostatic control but also provides an extra degree of freedom for manipulating the threshold voltage (VTH) and SS by separately tuning the top and back gate voltages, which are demonstrated in a logic inverter. Dynamic random access memory (DRAM) has a short retention time because of large OFF-state current in the Si MOSFET. Based on our DG MoS2-FETs, a DRAM unit cell with a long retention time of 1260 ms is realized. Large-scale isolated MoS2 DG-FETs based on CVD-synthesized continuous films are also demonstrated, which show potential applications for future wafer-scale digital and low-power electronics.

AB - We demonstrate dual-gated (DG) MoS2 field effect transistors (FETs) in which the degraded switching performance of multilayer MoS2 can be compensated by the DG structure. It produces large current density (>100 μA/μm for a monolayer), steep subthreshold swing (SS) (∼100 mV/dec for 5 nm thickness), and high on/off current ratio (>107 for 10 nm thickness). Such DG structure not only improves electrostatic control but also provides an extra degree of freedom for manipulating the threshold voltage (VTH) and SS by separately tuning the top and back gate voltages, which are demonstrated in a logic inverter. Dynamic random access memory (DRAM) has a short retention time because of large OFF-state current in the Si MOSFET. Based on our DG MoS2-FETs, a DRAM unit cell with a long retention time of 1260 ms is realized. Large-scale isolated MoS2 DG-FETs based on CVD-synthesized continuous films are also demonstrated, which show potential applications for future wafer-scale digital and low-power electronics.

KW - Dual-gate

KW - Dynamic random access memory cells

KW - Field-effect transistors

KW - Inverters

KW - MoS

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