Hardware Architecture of Layered Decoders for PLDPC-Hadamard Codes

Peng Wei Zhang; Sheng Jiang; Francis C.M. Lau; Chiu Wing Sham

doi:10.1109/TCSI.2022.3200687

Hardware Architecture of Layered Decoders for PLDPC-Hadamard Codes

Peng Wei Zhang, Sheng Jiang, Francis C.M. Lau, Chiu Wing Sham

The Hong Kong Polytechnic University

Research output: Journal article publication › Journal article › Academic research › peer-review

Abstract

Protograph-based low-density parity-check Hadamard codes (PLDPC-HCs) are a new type of ultimate-Shannon-limit-approaching codes. In this paper, we propose a hardware architecture for the PLDPC-HC layered decoders. The decoders consist mainly of random address memories, Hadamard sub-decoders and control logics. Two types of pipelined structures are presented and the latency and throughput of these two structures are derived. Implementation of the decoder design on an FPGA board shows that a throughput of 1.48 Gbps is achieved with a bit error rate (BER) of 10-5 at around Eb}/N0=-0.40 dB. The decoder can also achieve the same BER at Eb/N0=-1.14 dB with a reduced throughput of 0.20 Gbps.

Original language	English
Article number	9869760
Pages (from-to)	5325-5338
Number of pages	14
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	69
Issue number	12
DOIs	https://doi.org/10.1109/TCSI.2022.3200687
Publication status	Published - 1 Dec 2022

Keywords

Bit error rate
Codes
Computer architecture
Decoding
Hardware
Hardware design
layered decoding
Parity check codes
PLDPC-Hadamard code
Throughput

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

More information

10.1109/TCSI.2022.3200687

Cite this

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title = "Hardware Architecture of Layered Decoders for PLDPC-Hadamard Codes",

abstract = "Protograph-based low-density parity-check Hadamard codes (PLDPC-HCs) are a new type of ultimate-Shannon-limit-approaching codes. In this paper, we propose a hardware architecture for the PLDPC-HC layered decoders. The decoders consist mainly of random address memories, Hadamard sub-decoders and control logics. Two types of pipelined structures are presented and the latency and throughput of these two structures are derived. Implementation of the decoder design on an FPGA board shows that a throughput of 1.48 Gbps is achieved with a bit error rate (BER) of 10-5 at around Eb}/N0=-0.40 dB. The decoder can also achieve the same BER at Eb/N0=-1.14 dB with a reduced throughput of 0.20 Gbps.",

keywords = "Bit error rate, Codes, Computer architecture, Decoding, Hardware, Hardware design, layered decoding, Parity check codes, PLDPC-Hadamard code, Throughput",

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AU - Jiang, Sheng

AU - Lau, Francis C.M.

AU - Sham, Chiu Wing

PY - 2022/12/1

Y1 - 2022/12/1

N2 - Protograph-based low-density parity-check Hadamard codes (PLDPC-HCs) are a new type of ultimate-Shannon-limit-approaching codes. In this paper, we propose a hardware architecture for the PLDPC-HC layered decoders. The decoders consist mainly of random address memories, Hadamard sub-decoders and control logics. Two types of pipelined structures are presented and the latency and throughput of these two structures are derived. Implementation of the decoder design on an FPGA board shows that a throughput of 1.48 Gbps is achieved with a bit error rate (BER) of 10-5 at around Eb}/N0=-0.40 dB. The decoder can also achieve the same BER at Eb/N0=-1.14 dB with a reduced throughput of 0.20 Gbps.

AB - Protograph-based low-density parity-check Hadamard codes (PLDPC-HCs) are a new type of ultimate-Shannon-limit-approaching codes. In this paper, we propose a hardware architecture for the PLDPC-HC layered decoders. The decoders consist mainly of random address memories, Hadamard sub-decoders and control logics. Two types of pipelined structures are presented and the latency and throughput of these two structures are derived. Implementation of the decoder design on an FPGA board shows that a throughput of 1.48 Gbps is achieved with a bit error rate (BER) of 10-5 at around Eb}/N0=-0.40 dB. The decoder can also achieve the same BER at Eb/N0=-1.14 dB with a reduced throughput of 0.20 Gbps.

KW - Bit error rate

KW - Codes

KW - Computer architecture

KW - Decoding

KW - Hardware

KW - Hardware design

KW - layered decoding

KW - Parity check codes

KW - PLDPC-Hadamard code

KW - Throughput

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Hardware Architecture of Layered Decoders for PLDPC-Hadamard Codes

Abstract

Keywords

ASJC Scopus subject areas

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