Hardware Architecture of Layered Decoders for PLDPC-Hadamard Codes

Peng Wei Zhang, Sheng Jiang, Francis C.M. Lau, Chiu Wing Sham

Research output: Journal article publicationJournal articleAcademic researchpeer-review


Protograph-based low-density parity-check Hadamard codes (PLDPC-HCs) are a new type of ultimate-Shannon-limit-approaching codes. In this paper, we propose a hardware architecture for the PLDPC-HC layered decoders. The decoders consist mainly of random address memories, Hadamard sub-decoders and control logics. Two types of pipelined structures are presented and the latency and throughput of these two structures are derived. Implementation of the decoder design on an FPGA board shows that a throughput of 1.48 Gbps is achieved with a bit error rate (BER) of 10-5 at around Eb}/N0=-0.40 dB. The decoder can also achieve the same BER at Eb/N0=-1.14 dB with a reduced throughput of 0.20 Gbps.

Original languageEnglish
Article number9869760
Pages (from-to)5325-5338
Number of pages14
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number12
Publication statusPublished - 1 Dec 2022


  • Bit error rate
  • Codes
  • Computer architecture
  • Decoding
  • Hardware
  • Hardware design
  • layered decoding
  • Parity check codes
  • PLDPC-Hadamard code
  • Throughput

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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