Generic VLSI architecture for block-matching motion estimation algorithms

In this article, a generic VLSI architecture which is both programmable and scalable is proposed for block-matching motion estimation algorithms. Various motion estimation algorithms can be implemented using the proposed architecture by organizing the individual search positions (checking points) into checking vectors. A checking vector is processed in parallel by fully exploiting its data dependency. The optimal choice for the size of checking vector is discussed based on the design tradeoffs among processing speed, silicon area, and I/O bandwidth. Appropriate designs are recommended for various video applications.