Gain stage design based on narrow-width methodology in SOI technology

Denny T Y Cheung; Jack Lau; Philip Ching Ho Chan

Gain stage design based on narrow-width methodology in SOI technology

Denny T Y Cheung
, Jack Lau
, Philip Ching Ho Chan

Research output: Journal article publication › Conference article › Academic research › peer-review

Abstract

An optimized gain stage design strategy for operational amplifier in 2μm SOI technology is described. This approach is known as Narrow-Width Methodology (NWM), which offers a parasitic capacitance reduction in the significant node as compared with bulk technology because of the isolated mesa used in SOI technology. Therefore, when a 2-stage Miller compensated op amp is designed, a smaller Miller compensation capacitance (Cc) is employed to ensure stability. Moreover, the performance of unity-gain frequency (funity) is improved. Simulation results show that, when NWM is implemented in the output transistor, funity can be achieved up to 180MHz with Cc = 0.045pF in SOI technology, while funity equals 84MHz with Cc = 0.095pF in bulk counterparts.

Original language	English
Pages (from-to)	219-222
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	1
Publication status	Published - 1 Jan 1996
Externally published	Yes
Event	Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, United States Duration: 12 May 1996 → 15 May 1996

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Cite this

@article{5fd9406eacb149da82851fe23a4fe666,

title = "Gain stage design based on narrow-width methodology in SOI technology",

abstract = "An optimized gain stage design strategy for operational amplifier in 2μm SOI technology is described. This approach is known as Narrow-Width Methodology (NWM), which offers a parasitic capacitance reduction in the significant node as compared with bulk technology because of the isolated mesa used in SOI technology. Therefore, when a 2-stage Miller compensated op amp is designed, a smaller Miller compensation capacitance (Cc) is employed to ensure stability. Moreover, the performance of unity-gain frequency (funity) is improved. Simulation results show that, when NWM is implemented in the output transistor, funity can be achieved up to 180MHz with Cc = 0.045pF in SOI technology, while funity equals 84MHz with Cc = 0.095pF in bulk counterparts.",

author = "Cheung, \{Denny T Y\} and Jack Lau and Chan, \{Philip Ching Ho\}",

year = "1996",

month = jan,

day = "1",

language = "English",

volume = "1",

pages = "219--222",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "IEEE",

note = "Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) ; Conference date: 12-05-1996 Through 15-05-1996",

}

TY - JOUR

T1 - Gain stage design based on narrow-width methodology in SOI technology

AU - Cheung, Denny T Y

AU - Lau, Jack

AU - Chan, Philip Ching Ho

PY - 1996/1/1

Y1 - 1996/1/1

N2 - An optimized gain stage design strategy for operational amplifier in 2μm SOI technology is described. This approach is known as Narrow-Width Methodology (NWM), which offers a parasitic capacitance reduction in the significant node as compared with bulk technology because of the isolated mesa used in SOI technology. Therefore, when a 2-stage Miller compensated op amp is designed, a smaller Miller compensation capacitance (Cc) is employed to ensure stability. Moreover, the performance of unity-gain frequency (funity) is improved. Simulation results show that, when NWM is implemented in the output transistor, funity can be achieved up to 180MHz with Cc = 0.045pF in SOI technology, while funity equals 84MHz with Cc = 0.095pF in bulk counterparts.

AB - An optimized gain stage design strategy for operational amplifier in 2μm SOI technology is described. This approach is known as Narrow-Width Methodology (NWM), which offers a parasitic capacitance reduction in the significant node as compared with bulk technology because of the isolated mesa used in SOI technology. Therefore, when a 2-stage Miller compensated op amp is designed, a smaller Miller compensation capacitance (Cc) is employed to ensure stability. Moreover, the performance of unity-gain frequency (funity) is improved. Simulation results show that, when NWM is implemented in the output transistor, funity can be achieved up to 180MHz with Cc = 0.045pF in SOI technology, while funity equals 84MHz with Cc = 0.095pF in bulk counterparts.

UR - https://www.scopus.com/pages/publications/0029717201

M3 - Conference article

SN - 0271-4310

VL - 1

SP - 219

EP - 222

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4)

Y2 - 12 May 1996 through 15 May 1996

ER -

Gain stage design based on narrow-width methodology in SOI technology

Abstract

ASJC Scopus subject areas

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