Gain stage design based on narrow-width methodology in SOI technology

Denny T Y Cheung, Jack Lau, Philip Ching Ho Chan

Research output: Journal article publicationConference articleAcademic researchpeer-review

2 Citations (Scopus)

Abstract

An optimized gain stage design strategy for operational amplifier in 2μm SOI technology is described. This approach is known as Narrow-Width Methodology (NWM), which offers a parasitic capacitance reduction in the significant node as compared with bulk technology because of the isolated mesa used in SOI technology. Therefore, when a 2-stage Miller compensated op amp is designed, a smaller Miller compensation capacitance (Cc) is employed to ensure stability. Moreover, the performance of unity-gain frequency (funity) is improved. Simulation results show that, when NWM is implemented in the output transistor, funity can be achieved up to 180MHz with Cc = 0.045pF in SOI technology, while funity equals 84MHz with Cc = 0.095pF in bulk counterparts.
Original languageEnglish
Pages (from-to)219-222
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume1
Publication statusPublished - 1 Jan 1996
Externally publishedYes
EventProceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, United States
Duration: 12 May 199615 May 1996

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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