Fully depleted CMOS/SOI device design guidelines for low power applications

Srinivasa R. Banna, Philip Ching Ho Chan, Mansun Chan, Samuel K H Fung, Ping K. Ko

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

Abstract

In this paper we report the fully depleted CMOS/SOI device design guidelines for low power applications. Optimal technology, device and circuit parameters are discussed and compared with bulk CMOS based design. The differences and similarities are summarized. We believe this is the first such study to be reported.
Original languageEnglish
Title of host publicationInternational Symposium on Low Power Electronics and Design, Digest of Technical Papers
PublisherIEEE
Pages301-304
Number of pages4
Publication statusPublished - 1 Jan 1997
Externally publishedYes
EventProceedings of the 1997 International Symposium on Low Power Electronics and Design - Monterey, CA, United States
Duration: 18 Aug 199720 Aug 1997

Conference

ConferenceProceedings of the 1997 International Symposium on Low Power Electronics and Design
Country/TerritoryUnited States
CityMonterey, CA
Period18/08/9720/08/97

ASJC Scopus subject areas

  • Engineering(all)

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