Fully depleted CMOS/SOI device design guidelines for low-power applications

Srinivasa R. Banna, Philip Ching Ho Chan, Mansun Chan, Samuel K.H. Fung, Ping K. Ko

Research output: Journal article publicationJournal articleAcademic researchpeer-review

7 Citations (Scopus)

Abstract

We report the fully depleted (FD) CMOS/SOI device design guidelines for low-power applications. Optimal technology, device and circuit parameters are derived and compared with bulk CMOS based design. The differences and similarities are summarized. Device design guidelines using devices with L = 0.1 μm for FDSOI low-power applications are presented using an empirical drain saturation current model fitted to experimental data. The model is verified in the deep-submicron regime by two-dimensional (2-D) simulation. For L = 0.1 μm FDSOI low-power technology, optimum speed and lower-power occurs at Vdd= 3Vthand Vdd= 1.5Vth, respectively. Optimum buried oxide thickness is found to be between 300 and 400 nm for lower-power applications. Optimum transistor sizing is when the driver device capacitance is 0.3 times the total load capacitance. Similarly optimum gate oxide thickness is when the driver device gate capacitance is 0.2-0.6 times the total load capacitance for performance and 0.1-0.2 for low-power, respectively. Finally optimum stage ratio for driving large loads is around 2-4 for both high-performance and low-power.
Original languageEnglish
Pages (from-to)754-761
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume46
Issue number4
DOIs
Publication statusPublished - 1 Jan 1999
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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