Abstract
NAND flash memory has been widely used to build embedded devices such as smartphones and solid state drives (SSD) because of its high performance, low power consumption, great shock resistance and small form factor. However, its lifetime and performance are greatly constrained by partial page updates, which will lead to early depletion of free pages and frequent garbage collections. On the one hand, partial page updates are prevalent as a large portion of I/O does not modify file contents drastically. On the other hand, general-purpose cache usually does not specifically consider and eliminate duplicated contents, despite its popularity. In this paper, we propose a hybrid approach called FTL2, which employs both logging and mapping techniques in flash translation layer (FTL), to tackle the endurance problem and performance degradation caused by partial page updates in flash memory. FTL2logs the latest contents in a high-speed temporary storage, called Content Cache to handle partial page updates. Experimental results show that FTL2can greatly reduce page writes and postpone garbage collections with a small overhead.
Original language | English |
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Title of host publication | LCTES 2013 - Proceedings of the 2013 ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems |
Pages | 91-100 |
Number of pages | 10 |
DOIs | |
Publication status | Published - 23 Dec 2013 |
Event | 14th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools and Theory for Embedded Systems, LCTES 2013 - Seattle, WA, United States Duration: 20 Jun 2013 → 21 Jun 2013 |
Conference
Conference | 14th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools and Theory for Embedded Systems, LCTES 2013 |
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Country/Territory | United States |
City | Seattle, WA |
Period | 20/06/13 → 21/06/13 |
Keywords
- Caching
- Endurance
- Flash memory
- Flash translation layer
- Logging
- Partial page update
- Solid state drives
ASJC Scopus subject areas
- Software