Fault tolerant design for low power hierarchical search motion estimation algorithms

Charvi Dhoot; Vincent J. Mooney; Shubhajit Roy Chowdhury; Lap Pui Chau

doi:10.1109/VLSISoC.2011.6081649

Fault tolerant design for low power hierarchical search motion estimation algorithms

Charvi Dhoot
, Vincent J. Mooney
, Shubhajit Roy Chowdhury
, Lap Pui Chau

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

4 Citations (Scopus)

Abstract

Highly scaled CMOS devices are predicted to show probabilistic behavior due to process variations or the presence of noise sources such as thermal noise. Past research dealing with characterizing CMOS devices with probabilistic behavior has shown that computing via these devices, termed probabilistic computing, can help realize highly efficient circuits in terms of energy consumption. In this paper, we explore low power motion estimation, specifically low power hierarchical search algorithms for motion estimation, in the context of probabilistic computing. With the fault tolerant algorithm design (MC-TSS) proposed in this paper, we show that energy savings that can be realized with probabilistic computing increase to 70% versus 57% with the conventional algorithm (TSS), with minor impact on the quality of motion estimation. Furthermore, a 1.8 dB improvement in PSNR under the same energy savings of 70% for both algorithms is shown establishing the superior resilience of the proposed algorithm to probabilistic computing over the conventional algorithm.

Original language	English
Title of host publication	2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011
Pages	266-271
Number of pages	6
DOIs	https://doi.org/10.1109/VLSISoC.2011.6081649
Publication status	Published - Oct 2011
Externally published	Yes
Event	2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011 - Kowloon, Hong Kong Duration: 3 Oct 2011 → 5 Oct 2011

Publication series

Name	2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011

Conference

Conference	2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011
Country/Territory	Hong Kong
City	Kowloon
Period	3/10/11 → 5/10/11

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

fault-tolerant design
low power design
motion estimation
PCMOS architecture
probabilistic computing

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

More information

10.1109/VLSISoC.2011.6081649

Cite this

Dhoot, C., Mooney, V. J., Chowdhury, S. R., & Chau, L. P. (2011). Fault tolerant design for low power hierarchical search motion estimation algorithms. In 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011 (pp. 266-271). Article 6081649 (2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011). https://doi.org/10.1109/VLSISoC.2011.6081649

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title = "Fault tolerant design for low power hierarchical search motion estimation algorithms",

abstract = "Highly scaled CMOS devices are predicted to show probabilistic behavior due to process variations or the presence of noise sources such as thermal noise. Past research dealing with characterizing CMOS devices with probabilistic behavior has shown that computing via these devices, termed probabilistic computing, can help realize highly efficient circuits in terms of energy consumption. In this paper, we explore low power motion estimation, specifically low power hierarchical search algorithms for motion estimation, in the context of probabilistic computing. With the fault tolerant algorithm design (MC-TSS) proposed in this paper, we show that energy savings that can be realized with probabilistic computing increase to 70\% versus 57\% with the conventional algorithm (TSS), with minor impact on the quality of motion estimation. Furthermore, a 1.8 dB improvement in PSNR under the same energy savings of 70\% for both algorithms is shown establishing the superior resilience of the proposed algorithm to probabilistic computing over the conventional algorithm.",

keywords = "fault-tolerant design, low power design, motion estimation, PCMOS architecture, probabilistic computing",

author = "Charvi Dhoot and Mooney, \{Vincent J.\} and Chowdhury, \{Shubhajit Roy\} and Chau, \{Lap Pui\}",

year = "2011",

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booktitle = "2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011",

note = "2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011 ; Conference date: 03-10-2011 Through 05-10-2011",

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Dhoot, C, Mooney, VJ, Chowdhury, SR & Chau, LP 2011, Fault tolerant design for low power hierarchical search motion estimation algorithms. in 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011., 6081649, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, pp. 266-271, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, Kowloon, Hong Kong, 3/10/11. https://doi.org/10.1109/VLSISoC.2011.6081649

Fault tolerant design for low power hierarchical search motion estimation algorithms. / Dhoot, Charvi; Mooney, Vincent J.; Chowdhury, Shubhajit Roy et al.
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011. 2011. p. 266-271 6081649 (2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011).

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

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Dhoot C, Mooney VJ, Chowdhury SR, Chau LP. Fault tolerant design for low power hierarchical search motion estimation algorithms. In 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011. 2011. p. 266-271. 6081649. (2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011). doi: 10.1109/VLSISoC.2011.6081649

Fault tolerant design for low power hierarchical search motion estimation algorithms

Abstract

Publication series

Conference

UN SDGs

Keywords

ASJC Scopus subject areas

More information

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