Fault tolerant design for low power hierarchical search motion estimation algorithms

Charvi Dhoot, Vincent J. Mooney, Shubhajit Roy Chowdhury, Lap Pui Chau

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

4 Citations (Scopus)

Abstract

Highly scaled CMOS devices are predicted to show probabilistic behavior due to process variations or the presence of noise sources such as thermal noise. Past research dealing with characterizing CMOS devices with probabilistic behavior has shown that computing via these devices, termed probabilistic computing, can help realize highly efficient circuits in terms of energy consumption. In this paper, we explore low power motion estimation, specifically low power hierarchical search algorithms for motion estimation, in the context of probabilistic computing. With the fault tolerant algorithm design (MC-TSS) proposed in this paper, we show that energy savings that can be realized with probabilistic computing increase to 70% versus 57% with the conventional algorithm (TSS), with minor impact on the quality of motion estimation. Furthermore, a 1.8 dB improvement in PSNR under the same energy savings of 70% for both algorithms is shown establishing the superior resilience of the proposed algorithm to probabilistic computing over the conventional algorithm.

Original languageEnglish
Title of host publication2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011
Pages266-271
Number of pages6
DOIs
Publication statusPublished - Oct 2011
Externally publishedYes
Event2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011 - Kowloon, Hong Kong
Duration: 3 Oct 20115 Oct 2011

Publication series

Name2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011

Conference

Conference2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011
Country/TerritoryHong Kong
CityKowloon
Period3/10/115/10/11

Keywords

  • fault-tolerant design
  • low power design
  • motion estimation
  • PCMOS architecture
  • probabilistic computing

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'Fault tolerant design for low power hierarchical search motion estimation algorithms'. Together they form a unique fingerprint.

Cite this