Fabrication of Raised S/D Gate-All-Around Transistor and Gate Misalignment Analysis

Chunshan Yin, Philip Ching Ho Chan, Victor W C Chan

Research output: Journal article publicationJournal articleAcademic researchpeer-review

14 Citations (Scopus)

Abstract

In this letter, we present the implementation of a new raised source/drain (S/D) gate-all-around transistor (GAT). The device is fabricated on a bulk silicon wafer using a technique known as metal-induced-lateral-crystallization (MILC). Compared to conventional single gate MOSFETs, the GAT shows a smaller subthreshold-slope (SS), reduced drain-induced barrier lowering (DIBL), and almost doubled (187%) drive current. Gate misalignment is briefly studied using this novel device. It is found that the SS, DIBL, and drive current will degrade abruptly when gate misalignment is larger than 17% of gate length.
Original languageEnglish
Pages (from-to)658-660
Number of pages3
JournalIEEE Electron Device Letters
Volume24
Issue number10
DOIs
Publication statusPublished - 1 Oct 2003
Externally publishedYes

Keywords

  • Double-gate transistor
  • Gate misalignment
  • Gate-all-around transistor (GAT)
  • Metal-induced-lateral-crystallization (MILC)
  • Raised source/drain

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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