Fabrication of Raised S/D Gate-All-Around Transistor and Gate Misalignment Analysis

Chunshan Yin; Philip Ching Ho Chan; Victor W C Chan

doi:10.1109/LED.2003.817367

Fabrication of Raised S/D Gate-All-Around Transistor and Gate Misalignment Analysis

Chunshan Yin, Philip Ching Ho Chan, Victor W C Chan

Research output: Journal article publication › Journal article › Academic research › peer-review

16 Citations (Scopus)

Abstract

In this letter, we present the implementation of a new raised source/drain (S/D) gate-all-around transistor (GAT). The device is fabricated on a bulk silicon wafer using a technique known as metal-induced-lateral-crystallization (MILC). Compared to conventional single gate MOSFETs, the GAT shows a smaller subthreshold-slope (SS), reduced drain-induced barrier lowering (DIBL), and almost doubled (187%) drive current. Gate misalignment is briefly studied using this novel device. It is found that the SS, DIBL, and drive current will degrade abruptly when gate misalignment is larger than 17% of gate length.

Original language	English
Pages (from-to)	658-660
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	24
Issue number	10
DOIs	https://doi.org/10.1109/LED.2003.817367
Publication status	Published - 1 Oct 2003
Externally published	Yes

Keywords

Double-gate transistor
Gate misalignment
Gate-all-around transistor (GAT)
Metal-induced-lateral-crystallization (MILC)
Raised source/drain

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

More information

10.1109/LED.2003.817367

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@article{16a25e297e454ef998badb5362799674,

title = "Fabrication of Raised S/D Gate-All-Around Transistor and Gate Misalignment Analysis",

abstract = "In this letter, we present the implementation of a new raised source/drain (S/D) gate-all-around transistor (GAT). The device is fabricated on a bulk silicon wafer using a technique known as metal-induced-lateral-crystallization (MILC). Compared to conventional single gate MOSFETs, the GAT shows a smaller subthreshold-slope (SS), reduced drain-induced barrier lowering (DIBL), and almost doubled (187%) drive current. Gate misalignment is briefly studied using this novel device. It is found that the SS, DIBL, and drive current will degrade abruptly when gate misalignment is larger than 17% of gate length.",

keywords = "Double-gate transistor, Gate misalignment, Gate-all-around transistor (GAT), Metal-induced-lateral-crystallization (MILC), Raised source/drain",

author = "Chunshan Yin and Chan, {Philip Ching Ho} and Chan, {Victor W C}",

year = "2003",

month = oct,

day = "1",

doi = "10.1109/LED.2003.817367",

language = "English",

volume = "24",

pages = "658--660",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "IEEE",

number = "10",

}

TY - JOUR

T1 - Fabrication of Raised S/D Gate-All-Around Transistor and Gate Misalignment Analysis

AU - Yin, Chunshan

AU - Chan, Philip Ching Ho

AU - Chan, Victor W C

PY - 2003/10/1

Y1 - 2003/10/1

N2 - In this letter, we present the implementation of a new raised source/drain (S/D) gate-all-around transistor (GAT). The device is fabricated on a bulk silicon wafer using a technique known as metal-induced-lateral-crystallization (MILC). Compared to conventional single gate MOSFETs, the GAT shows a smaller subthreshold-slope (SS), reduced drain-induced barrier lowering (DIBL), and almost doubled (187%) drive current. Gate misalignment is briefly studied using this novel device. It is found that the SS, DIBL, and drive current will degrade abruptly when gate misalignment is larger than 17% of gate length.

AB - In this letter, we present the implementation of a new raised source/drain (S/D) gate-all-around transistor (GAT). The device is fabricated on a bulk silicon wafer using a technique known as metal-induced-lateral-crystallization (MILC). Compared to conventional single gate MOSFETs, the GAT shows a smaller subthreshold-slope (SS), reduced drain-induced barrier lowering (DIBL), and almost doubled (187%) drive current. Gate misalignment is briefly studied using this novel device. It is found that the SS, DIBL, and drive current will degrade abruptly when gate misalignment is larger than 17% of gate length.

KW - Double-gate transistor

KW - Gate misalignment

KW - Gate-all-around transistor (GAT)

KW - Metal-induced-lateral-crystallization (MILC)

KW - Raised source/drain

UR - http://www.scopus.com/inward/record.url?scp=0141952861&partnerID=8YFLogxK

U2 - 10.1109/LED.2003.817367

DO - 10.1109/LED.2003.817367

M3 - Journal article

SN - 0741-3106

VL - 24

SP - 658

EP - 660

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 10

ER -

Fabrication of Raised S/D Gate-All-Around Transistor and Gate Misalignment Analysis

Abstract

Keywords

ASJC Scopus subject areas

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