Extremely fast simulator for decoding LDPC codes

S. F. Yau, T. L. Wong, Chung Ming Lau

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

4 Citations (Scopus)

Abstract

Decoding low-density parity-check (LDPC) codes requires a lot of computation time, particularly when bit error rates as low as 109 are needed. In this paper, we improve the simulation speed by making use of an inexpensive graphics processing unit (GPU). A dedicated program is written to utilize the hardware resources in the GPU to decode LDPC codes in a parallel manner. Codes with rate 1/2 and length 2, 304 and 10, 008 are simulated by both GPU and central processing unit (CPU). We also show the average iteration time when LDPC codes with length 15, 000 and 20, 000 are simulated.
Original languageEnglish
Title of host publication13th International Conference on Advanced Communication Technology
Subtitle of host publicationSmart Service Innovation through Mobile Interactivity, ICACT 2011, Proceeding
Pages635-639
Number of pages5
Publication statusPublished - 11 May 2011
Event13th International Conference on Advanced Communication Technology: Smart Service Innovation through Mobile Interactivity, ICACT 2011 - Gangwon-Do, Korea, Republic of
Duration: 13 Feb 201116 Feb 2011

Conference

Conference13th International Conference on Advanced Communication Technology: Smart Service Innovation through Mobile Interactivity, ICACT 2011
CountryKorea, Republic of
CityGangwon-Do
Period13/02/1116/02/11

Keywords

  • Fast decoding
  • GPU computing
  • LDPC codes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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