TY - GEN
T1 - Evaluation of Temperature-Humidity-Reverse Bias Robustness of 3rd Generation 650V Class 4H-SiC Discrete Power MOSFET Devices
AU - Waseem, Muhammad
AU - Ibrahim, Mesfin Seid
AU - Abbas, Waseem
AU - Lu, Chang
AU - Yuluo, Hou
AU - Lee, Hiu Hung
AU - Hao, Zhang
AU - Loo, Ka Hong
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023/10
Y1 - 2023/10
N2 - In this study, 3rd generation 650V class 4H-SiC power MOSFET discrete devices from four different global manufacturers are stressed using a high-voltage, high-humidity, high-temperature, reverse bias (HV-H3TRB) test to assess their reliability. It is found that the moisture ingress is the root cause of the failure of test samples. Post-failure analysis results have displayed drain-source junction and gate oxide insulation layer breakdown as well as moisture-induced electrochemical migration of contaminated metals. TCAD simulation is performed to explore the effect of differences in the distribution of the electric field around the gate stack on the reliability of test samples. Our simulation and experimental investigation findings indicate that the pre-existing surface and bulk defects/voids, drain-source junction breakdown voltage margin ratio, gate-oxide thickness, and device internal structure design should be considered when designing, processing, fabricating, and packaging the 3rd generation SiC MOSFETs. This would improve their temperature-humidity reverse bias robustness for humidity-critical applications.
AB - In this study, 3rd generation 650V class 4H-SiC power MOSFET discrete devices from four different global manufacturers are stressed using a high-voltage, high-humidity, high-temperature, reverse bias (HV-H3TRB) test to assess their reliability. It is found that the moisture ingress is the root cause of the failure of test samples. Post-failure analysis results have displayed drain-source junction and gate oxide insulation layer breakdown as well as moisture-induced electrochemical migration of contaminated metals. TCAD simulation is performed to explore the effect of differences in the distribution of the electric field around the gate stack on the reliability of test samples. Our simulation and experimental investigation findings indicate that the pre-existing surface and bulk defects/voids, drain-source junction breakdown voltage margin ratio, gate-oxide thickness, and device internal structure design should be considered when designing, processing, fabricating, and packaging the 3rd generation SiC MOSFETs. This would improve their temperature-humidity reverse bias robustness for humidity-critical applications.
KW - Accelerated degradation test
KW - Humidity
KW - HV-H3TRB test
KW - MOSFET aging
KW - Reliability
KW - SiC Power MOSFETs
UR - http://www.scopus.com/inward/record.url?scp=85190389446&partnerID=8YFLogxK
U2 - 10.1109/IIRW59383.2023.10477692
DO - 10.1109/IIRW59383.2023.10477692
M3 - Conference article published in proceeding or book
AN - SCOPUS:85190389446
T3 - IEEE International Integrated Reliability Workshop Final Report
BT - 2023 IEEE International Integrated Reliability Workshop, IIRW 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 IEEE International Integrated Reliability Workshop, IIRW 2023
Y2 - 8 October 2023 through 12 October 2023
ER -