Abstract
The energy consumption profiling of the H.264 video decoder on VLIW embedded processors using the Trimaran simulator is conducted. Based on this study, we observe that the branch operations in the quarter-pixel (QP) interpolation and the DCT slow down the issue rate of the VLIW processors. Then, several new instruction architecture sets are proposed to address this issue. These new instructions can be used to speedup the issue rate, and reduce the total energy consumption. Finally, experimental results of the proposed instruction-level power-efficient strategies on the TI C6416 processor are reported and discussed.
| Original language | English |
|---|---|
| Article number | 02 |
| Pages (from-to) | 9-20 |
| Number of pages | 12 |
| Journal | Proceedings of SPIE - The International Society for Optical Engineering |
| Volume | 5683 |
| DOIs | |
| Publication status | Published - 21 Jul 2005 |
| Externally published | Yes |
| Event | Proceedings of SPIE-IS and T Electronic Imaging - Embedded Processors for Multimedia and Communications II - San Jose, CA, United States Duration: 17 Jan 2005 → 18 Jan 2005 |
Keywords
- Embedded processor
- Energy optimization
- H.264
- VLIW
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Computer Science Applications
- Applied Mathematics
- Electrical and Electronic Engineering
