Conventional PFC power supplies employ two cascading stages that deal separately with PFC and voltage regulation. Since power is processed serially by two power stages, the efficiency is limited. In this paper a PFC power supply with improved efficiency is proposed. This circuit makes use of a parallel configuration that reduces unnecessary processing of all power by two stages serially. The circuit is derived from consideration of the power flow between the input, the load and the storage capacitor. A specific circuit implementation is described and the test results are reported.
|Number of pages||6|
|Journal||PESC Record - IEEE Annual Power Electronics Specialists Conference|
|Publication status||Published - 1 Dec 1999|
|Event||Proceedings of the 1999 30th Annual IEEE Power Electronics Specialists Conference (PESC'99) - Charleston, SC, United States|
Duration: 27 Jun 1999 → 1 Jul 1999
ASJC Scopus subject areas
- Electrical and Electronic Engineering