Efficient multiplier structure for realization of the discrete cosine transform

Lap Pui Chau, Wan Chi Siu

Research output: Journal article publicationJournal articleAcademic researchpeer-review

7 Citations (Scopus)


This paper presents an efficient serial-parallel multiplier algorithm that realizes the input data bit-serially, for implementation of the discrete cosine transform (DCT), which realizes the input data bit-serially. First, the DCT equation is split into a few groups of equations by using some mathematical techniques, and index tables are constructed to facilitate efficient data permutations. A new formulation of the DCT is then derived. Second, we represent the cosine coefficient in binary form and realize multiplications using a new serial-parallel multiplier architecture that results in a simple structure for VLSI realization.

Original languageEnglish
Pages (from-to)527-536
Number of pages10
JournalSignal Processing: Image Communication
Issue number7
Publication statusPublished - Aug 2003


  • Discrete cosine transform
  • Serial-Parallel multiplier algorithm

ASJC Scopus subject areas

  • Software
  • Signal Processing
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering


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