Effects of a Gate-Electrode/Gate-Dielectric Interlayer on Carrier Mobility for Pentacene Organic Thin-Film Transistors

Yuan Xiao Ma, Wing Man Tang, Pui To Lai

Research output: Journal article publicationJournal articleAcademic researchpeer-review

1 Citation (Scopus)

Abstract

Bottom-gated pentacene organic thin-film transistors with LaTiON gate dielectrics annealed at two different temperatures are fabricated on n+Si wafers. Although atomic-force microscopyresults indicate a smoother dielectric surface and larger pentacene grains for the sample annealed at 400 °C, this sample shows lower carrier mobility than the one annealed at 200 °C. Moreover, the crystallinity of the gate dielectrics is not a key factor in the degradation of the carrier mobility because both dielectrics remain amorphous according to TEM. However, the TEM results show that the sample annealed at 400 °C has a thicker dielectric/Si-gate interlayer. The resultant increase in gate electrode-to-dielectric distance weakens the gate screening of the remote phonon scattering, thereby degrading the mobility of the carriers in the pentacene channel. This effect can be further supported by two similar samples fabricated on n-Si wafers, in which the gate electrode with lower electron concentration has a reduced screening effect on the remote phonon scattering and results in a larger reduction in mobility for the 400 °C-annealed sample with thicker interlayer.

Original languageEnglish
Article number8447279
Pages (from-to)1516-1519
Number of pages4
JournalIEEE Electron Device Letters
Volume39
Issue number10
DOIs
Publication statusPublished - 1 Oct 2018

Keywords

  • high-k dielectric
  • Organic thin-film transistor
  • phonon scattering
  • remote interlayer

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this