DPA: A data pattern aware error prevention technique for NAND flash lifetime extension

Jie Guo; Zhijie Chen; Danghui Wang; Zili Shao; Yiran Chen

doi:10.1109/ASPDAC.2014.6742955

DPA: A data pattern aware error prevention technique for NAND flash lifetime extension

Jie Guo, Zhijie Chen, Danghui Wang, Zili Shao, Yiran Chen

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

28 Citations (Scopus)

Abstract

The recent research reveals that the bit error rate of a NAND flash cell is highly dependent on the stored data patterns. In this work, we propose Data Pattern Aware (DPA) error protection technique to extend the lifespan of NAND flash based storage systems (NFSS). DPA manipulates the ratio of 1's and 0's in the stored data to minimize occurrence of the data patterns which are susceptible to bit error noise. Consequently, the NAND flash cell bit error rate is reduced, leading to system endurance extension. Our simulation result shows that, with marginal hardware and power overhead, DPA scheme can increase the NFSS lifetime by up to 4×, offering a complementing solution to other lifetime enhancement techniques like wear-leveling.

Original language	English
Title of host publication	2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings
Pages	592-597
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2014.6742955
Publication status	Published - 27 Mar 2014
Event	2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Suntec, Singapore Duration: 20 Jan 2014 → 23 Jan 2014

Conference

Conference	2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014
Country/Territory	Singapore
City	Suntec
Period	20/01/14 → 23/01/14

ASJC Scopus subject areas

Electrical and Electronic Engineering
Computer Science Applications
Computer Graphics and Computer-Aided Design

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10.1109/ASPDAC.2014.6742955

Cite this

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title = "DPA: A data pattern aware error prevention technique for NAND flash lifetime extension",

abstract = "The recent research reveals that the bit error rate of a NAND flash cell is highly dependent on the stored data patterns. In this work, we propose Data Pattern Aware (DPA) error protection technique to extend the lifespan of NAND flash based storage systems (NFSS). DPA manipulates the ratio of 1's and 0's in the stored data to minimize occurrence of the data patterns which are susceptible to bit error noise. Consequently, the NAND flash cell bit error rate is reduced, leading to system endurance extension. Our simulation result shows that, with marginal hardware and power overhead, DPA scheme can increase the NFSS lifetime by up to 4×, offering a complementing solution to other lifetime enhancement techniques like wear-leveling.",

author = "Jie Guo and Zhijie Chen and Danghui Wang and Zili Shao and Yiran Chen",

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Guo, J, Chen, Z, Wang, D, Shao, Z & Chen, Y 2014, DPA: A data pattern aware error prevention technique for NAND flash lifetime extension. in 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings., 6742955, pp. 592-597, 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014, Suntec, Singapore, 20/01/14. https://doi.org/10.1109/ASPDAC.2014.6742955

DPA: A data pattern aware error prevention technique for NAND flash lifetime extension. / Guo, Jie; Chen, Zhijie; Wang, Danghui et al.
2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings. 2014. p. 592-597 6742955.

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

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AB - The recent research reveals that the bit error rate of a NAND flash cell is highly dependent on the stored data patterns. In this work, we propose Data Pattern Aware (DPA) error protection technique to extend the lifespan of NAND flash based storage systems (NFSS). DPA manipulates the ratio of 1's and 0's in the stored data to minimize occurrence of the data patterns which are susceptible to bit error noise. Consequently, the NAND flash cell bit error rate is reduced, leading to system endurance extension. Our simulation result shows that, with marginal hardware and power overhead, DPA scheme can increase the NFSS lifetime by up to 4×, offering a complementing solution to other lifetime enhancement techniques like wear-leveling.

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DPA: A data pattern aware error prevention technique for NAND flash lifetime extension

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