Doped low-density parity-check codes

Yong Li; Rui Liu; Xianlong Jiao; Youqiang Hu; Zhen Luo; Francis C.M. Lau

doi:10.1016/j.dcan.2022.11.013

Doped low-density parity-check codes

Yong Li, Rui Liu, Xianlong Jiao, Youqiang Hu, Zhen Luo, Francis C.M. Lau

Research output: Journal article publication › Journal article › Academic research › peer-review

Abstract

In this paper, we propose a doping approach to lower the error floor of Low-Density Parity-Check (LDPC) codes. The doping component is a short block code in which the information bits are selected from the coded bits of the dominant trapping sets of the LDPC code. Accordingly, an algorithm for selecting the information bits of the short code is proposed, and a specific two-stage decoding algorithm is presented. Simulation results demonstrate that the proposed doped LDPC code achieves up to 2.0 dB gain compared with the original LDPC code at a frame error rate of 10⁻⁶. Furthermore, the proposed design can lower the error floor of original LDPC codes.

Original language	English
Pages (from-to)	217-226
Number of pages	10
Journal	Digital Communications and Networks
Volume	10
Issue number	1
DOIs	https://doi.org/10.1016/j.dcan.2022.11.013
Publication status	Published - Feb 2024

Keywords

Doped LDPC codes
LDPC codes
Quadratic residue codes
Tanner graph
Trapping sets

ASJC Scopus subject areas

Hardware and Architecture
Computer Networks and Communications

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10.1016/j.dcan.2022.11.013

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abstract = "In this paper, we propose a doping approach to lower the error floor of Low-Density Parity-Check (LDPC) codes. The doping component is a short block code in which the information bits are selected from the coded bits of the dominant trapping sets of the LDPC code. Accordingly, an algorithm for selecting the information bits of the short code is proposed, and a specific two-stage decoding algorithm is presented. Simulation results demonstrate that the proposed doped LDPC code achieves up to 2.0 dB gain compared with the original LDPC code at a frame error rate of 10−6. Furthermore, the proposed design can lower the error floor of original LDPC codes.",

keywords = "Doped LDPC codes, LDPC codes, Quadratic residue codes, Tanner graph, Trapping sets",

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AU - Li, Yong

AU - Liu, Rui

AU - Jiao, Xianlong

AU - Hu, Youqiang

AU - Luo, Zhen

AU - Lau, Francis C.M.

PY - 2024/2

Y1 - 2024/2

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AB - In this paper, we propose a doping approach to lower the error floor of Low-Density Parity-Check (LDPC) codes. The doping component is a short block code in which the information bits are selected from the coded bits of the dominant trapping sets of the LDPC code. Accordingly, an algorithm for selecting the information bits of the short code is proposed, and a specific two-stage decoding algorithm is presented. Simulation results demonstrate that the proposed doped LDPC code achieves up to 2.0 dB gain compared with the original LDPC code at a frame error rate of 10−6. Furthermore, the proposed design can lower the error floor of original LDPC codes.

KW - Doped LDPC codes

KW - LDPC codes

KW - Quadratic residue codes

KW - Tanner graph

KW - Trapping sets

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Doped low-density parity-check codes

Abstract

Keywords

ASJC Scopus subject areas

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