Digital Current Control for Permanent Magnet Synchronous Machine Drives with Fractional-Step Computation Delay

This article proposes a digital current controller for permanent magnet synchronous machine (PMSM) drives, specifically addressing scenarios where the computation delay is a fraction of the sampling period. The fractional-step computation delay (FSCD) introduces a transmission zero in the discrete-time PMSM model, causing undesirable coupling between dq-axis currents. The proposed controller employs complementary zero assignment to ensure decoupled current dynamics and incorporates a dual-update strategy to enhance transient performance. Active resistance (AR) is also utilized to improve disturbance rejection. The controller integrates seamlessly with asymmetrical regular-sampled pulsewidth modulation (PWM) and supports operation at lower sampling frequencies without compromising performance, thereby reducing computational burden. This makes it particularly suitable for transportation electrification applications demanding high switching frequencies and precise current regulation. Experimental results from a laboratory-based PMSM test setup validate the effectiveness of the proposed method.