Design of low power differential logic using adiabatic switching technique

Chun Keung Lo; Philip Ching Ho Chan

Design of low power differential logic using adiabatic switching technique

Chun Keung Lo, Philip Ching Ho Chan

Research output: Journal article publication › Conference article › Academic research › peer-review

Abstract

This paper presents a new adiabatic circuit technique called adiabatic differential cascode voltage switch with complementary pass-transistor logic tree (ADCPL). Power reduction is achieved by recovering the energy in the recover phase of the supply clock. Energy dissipation comparison with other logic circuits is performed. Simulation shows that for a pipelined ADCPL carry lookahead adder, a power reduction of 50% to 70% can be achieved over static CMOS case within a practical operation frequency range.

Original language	English
Pages (from-to)	33-36
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
Publication status	Published - 1 Jan 1998
Externally published	Yes
Event	Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, United States Duration: 31 May 1998 → 3 Jun 1998

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Cite this

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title = "Design of low power differential logic using adiabatic switching technique",

abstract = "This paper presents a new adiabatic circuit technique called adiabatic differential cascode voltage switch with complementary pass-transistor logic tree (ADCPL). Power reduction is achieved by recovering the energy in the recover phase of the supply clock. Energy dissipation comparison with other logic circuits is performed. Simulation shows that for a pipelined ADCPL carry lookahead adder, a power reduction of 50% to 70% can be achieved over static CMOS case within a practical operation frequency range.",

author = "Lo, {Chun Keung} and Chan, {Philip Ching Ho}",

year = "1998",

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AU - Lo, Chun Keung

AU - Chan, Philip Ching Ho

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N2 - This paper presents a new adiabatic circuit technique called adiabatic differential cascode voltage switch with complementary pass-transistor logic tree (ADCPL). Power reduction is achieved by recovering the energy in the recover phase of the supply clock. Energy dissipation comparison with other logic circuits is performed. Simulation shows that for a pipelined ADCPL carry lookahead adder, a power reduction of 50% to 70% can be achieved over static CMOS case within a practical operation frequency range.

AB - This paper presents a new adiabatic circuit technique called adiabatic differential cascode voltage switch with complementary pass-transistor logic tree (ADCPL). Power reduction is achieved by recovering the energy in the recover phase of the supply clock. Energy dissipation comparison with other logic circuits is performed. Simulation shows that for a pipelined ADCPL carry lookahead adder, a power reduction of 50% to 70% can be achieved over static CMOS case within a practical operation frequency range.

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M3 - Conference article

SN - 0271-4310

VL - 2

SP - 33

EP - 36

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6)

Y2 - 31 May 1998 through 3 June 1998

ER -

Design of low power differential logic using adiabatic switching technique

Abstract

ASJC Scopus subject areas

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