TY - GEN
T1 - Design of a high-throughput low-latency extended golay decoder
AU - Zhang, Pengwei
AU - Lau, Francis C.M.
AU - Sham, Chiu W.
PY - 2017/12/11
Y1 - 2017/12/11
N2 - In this paper, we propose a parallel architecture of the imperfect maximum likelihood decoding (IMLD) method, called PIMLD. It is further implemented onto an FPGA and applied to decode the (24,12,8) extended Golay code. Experimental results show that the proposed PIMLD decoder achieves 12.0 Gb/s throughput at 500 MHz frequency. Moreover, the latency for the decoder is only 5 clock cycles.
AB - In this paper, we propose a parallel architecture of the imperfect maximum likelihood decoding (IMLD) method, called PIMLD. It is further implemented onto an FPGA and applied to decode the (24,12,8) extended Golay code. Experimental results show that the proposed PIMLD decoder achieves 12.0 Gb/s throughput at 500 MHz frequency. Moreover, the latency for the decoder is only 5 clock cycles.
UR - http://www.scopus.com/inward/record.url?scp=85050590628&partnerID=8YFLogxK
U2 - 10.23919/APCC.2017.8304002
DO - 10.23919/APCC.2017.8304002
M3 - Conference article published in proceeding or book
AN - SCOPUS:85050590628
T3 - 2017 23rd Asia-Pacific Conference on Communications: Bridging the Metropolitan and the Remote, APCC 2017
SP - 1
EP - 4
BT - 2017 23rd Asia-Pacific Conference on Communications
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 23rd Asia-Pacific Conference on Communications, APCC 2017
Y2 - 11 December 2017 through 13 December 2017
ER -