Design of a high-throughput low-latency extended golay decoder

Pengwei Zhang, Francis C.M. Lau, Chiu W. Sham

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

1 Citation (Scopus)


In this paper, we propose a parallel architecture of the imperfect maximum likelihood decoding (IMLD) method, called PIMLD. It is further implemented onto an FPGA and applied to decode the (24,12,8) extended Golay code. Experimental results show that the proposed PIMLD decoder achieves 12.0 Gb/s throughput at 500 MHz frequency. Moreover, the latency for the decoder is only 5 clock cycles.

Original languageEnglish
Title of host publication2017 23rd Asia-Pacific Conference on Communications
Subtitle of host publicationBridging the Metropolitan and the Remote, APCC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)9781740523905
Publication statusPublished - 11 Dec 2017
Event23rd Asia-Pacific Conference on Communications, APCC 2017 - Perth, Australia
Duration: 11 Dec 201713 Dec 2017

Publication series

Name2017 23rd Asia-Pacific Conference on Communications: Bridging the Metropolitan and the Remote, APCC 2017


Conference23rd Asia-Pacific Conference on Communications, APCC 2017

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Signal Processing

Cite this