TY - GEN
T1 - Design of a high-performance pyramid architecture
AU - Ercan, M. Fikret
AU - Fung, Y. F.
PY - 1995/5
Y1 - 1995/5
N2 - In this paper, we are going to introduce a pyramid architecture, which we are currently constructing for computer vision applications. Some of the architectural features of the system is its linear array interconnections, reconfigurable architecture and its design without top-down control mechanism. The system is targeted to use in real time image processing applications, so that high performance processors are used during construction. It has three processing layers for three different stages of image processing. Each layer has direct access to image source. Architectural properties of the system, its control mechanism and expected performance, are outlined in the following sections.
AB - In this paper, we are going to introduce a pyramid architecture, which we are currently constructing for computer vision applications. Some of the architectural features of the system is its linear array interconnections, reconfigurable architecture and its design without top-down control mechanism. The system is targeted to use in real time image processing applications, so that high performance processors are used during construction. It has three processing layers for three different stages of image processing. Each layer has direct access to image source. Architectural properties of the system, its control mechanism and expected performance, are outlined in the following sections.
UR - http://www.scopus.com/inward/record.url?scp=0029233099&partnerID=8YFLogxK
M3 - Conference article published in proceeding or book
AN - SCOPUS:0029233099
SN - 0891418587
T3 - Proceedings of SPIE - The International Society for Optical Engineering
SP - 482
EP - 488
BT - Proceedings of SPIE - The International Society for Optical Engineering
PB - Society of Photo-Optical Instrumentation Engineers
T2 - Visual Communications and Image Processing '95
Y2 - 24 May 1995 through 26 May 1995
ER -