Abstract
This paper proposes a design methodology for specific network-on-chip (ASNoC). The methodology generate optimized hierarchical ASNoC and a corresponding shared memory for different applications. It uses communication traces for cycle-accurate performance for quick evaluation, and is based on floorplan to power and area. The methodology can be easily into current hardware/software codesign flow. Using methodology, we generated an ASNoC for a H.264 HDTV SoC. We compared the ASNoC with MIT's RAW in performance, power, and area in detail. The results show that the ASNoC provide substantial in power, performance, and cost compared to topology NoC. In the H.264 HDTV decoder SoC, the uses 39% less power, 59% less silicon area, 74% less area, 63% less switch capacity, and 69% less link capacity achieve 2X performance compared to the RAW network.
Original language | English |
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Title of host publication | 2008 International SoC Design Conference, ISOCC 2008 |
Volume | 1 |
DOIs | |
Publication status | Published - 1 Dec 2008 |
Event | 2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of Duration: 24 Nov 2008 → 25 Nov 2008 |
Conference
Conference | 2008 International SoC Design Conference, ISOCC 2008 |
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Country/Territory | Korea, Republic of |
City | Busan |
Period | 24/11/08 → 25/11/08 |
Keywords
- Embedded syste
- Methodology
- Network-on-chip
- System-on-chip
ASJC Scopus subject areas
- Hardware and Architecture
- Software