Demand-based block-level address mapping in large-scale NAND flash storage systems

Zhiwei Qin, Yi Wang, Duo Liu, Zili Shao

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

59 Citations (Scopus)

Abstract

The increasing capacity of NAND flash memory leads to large RAM footprint on address mapping in the Flash Translation Layer (FTL) design. This paper proposes a novel Demand-based block-level Address mapping scheme with two-level Caching mechanism (DAC) for large-scale NAND flash storage systems. The objective is to reduce RAM footprint without sacrificing too much system response time. In our technique, the block-level address mapping table is stored in fixed pages (called translation pages) in the flash memory. Considering temporal locality that workloads exhibit, we maintain one cache in RAM to store the on-demand block-level address mapping information. Meanwhile, by exploring both spatial locality and access frequency of workloads with another two caches, the second-level cache is designed to cache selected translation pages into RAM. In such a way, address mapping information for both sequential accesses and most-frequently-accessed translation pages can be found in the cache, and therefore, the system response time can be improved. We conduct experiments on a mixture of real-world and synthetic traces. The experimental results show that our technique can significantly reduce the RAM footprint while the average response time is kept well under control. Moreover, our technique shows big improvement on wear-leveling compared with the previous work.
Original languageEnglish
Title of host publicationEmbedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'10
Pages173-182
Number of pages10
DOIs
Publication statusPublished - 1 Dec 2010
Event6th Embedded Systems Week, ESWEEK 2010 - 8th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS'10 - Scottsdale, AZ, United States
Duration: 24 Oct 201029 Oct 2010

Conference

Conference6th Embedded Systems Week, ESWEEK 2010 - 8th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS'10
Country/TerritoryUnited States
CityScottsdale, AZ
Period24/10/1029/10/10

Keywords

  • Block-level mapping
  • NAND flash
  • Two-level cache

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

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