Data-Pattern-Aware Error Prevention Technique to Improve System Reliability

Jie Guo, Danghui Wang, Zili Shao, Yiran Chen

Research output: Journal article publicationJournal articleAcademic researchpeer-review

11 Citations (Scopus)


Program disturb, read disturb, and retention time noise are identified as three major contributors to multilevel cell (MLC) NAND flash memory bit errors. With program/erase cycling and technology scaling, bit error rate (BER) of MLC NAND flash memory rapidly increases. Previous works revealed that BER is heavily dependent on data patterns. Based on this observation, we propose data-pattern-aware (DPA) error protection technique to extend the lifespan of NAND flash-based storage systems. DPA manipulates the ratios of 0's and 1's in the stored data to reduce the probability of the data patterns, which are susceptible to device noises. By minimizing the vulnerable data patterns, our scheme can effectively reduce the BER and improves the system endurance. Our DPA scheme also incorporates a data management scheme to minimize the redundancy-induced performance overhead. Simulation results show that our scheme can increase flash system life expectancy by up to 4 ×.
Original languageEnglish
Article number7814316
Pages (from-to)1433-1443
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number4
Publication statusPublished - 1 Apr 2017


  • Flash memories
  • reliability
  • solid state disk (SSD)
  • storage management

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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