Damping controller design for FACTS device Part II: Controller structure and parameter optimisation

A new approach to solve the instability problem, due to the interaction between the damping controller and FACTS thyristor circuit, is introduced. FACTS instability mode is detected in the design process so the structure and setting of the damping controller is achieved through a combined sensitivity coefficient (CSC) which automatically takes into account the damping of both the interarea and FACTS modes. Traditionally, a lead/lag circuit is regarded as providing phase compensation for a controller so a few lead/lag stages would be needed to achieve sufficient phase shifts at the frequency of concern. In this paper, however, a different viewpoint will be offered. From time constant synthesis, three different objectives of a proper designed lead/lag circuit are highlighted, but the dominant one is associated with gain compensation, not with phase compensation. Moreover, the required number of stages, the choice of lead or lag compensation, and the selection of the time setting ranges are all clearly indicated from the synthesis.