Constructing high-rate scale-free LDPC codes

X. Zheng; Chung Ming Lau; Chi Kong Tse

doi:10.1109/ISCAS.2010.5537734

Constructing high-rate scale-free LDPC codes

X. Zheng
, Chung Ming Lau
, Chi Kong Tse

The Hong Kong Polytechnic University

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

Abstract

Low-density parity-check (LDPC) codes with scale-free (SF) symbol-node degree distribution have been shown to provide very good error performance. When the code rate becomes high, however, there will be a lot of degree-2 symbol nodes in the "pure" SF-LDPC codes. As a consequence, when the codes are constructed by connecting the symbol nodes with the check nodes, many small-size cycles will be formed. Such small-cycles will degrade the error performance of the codes. In this paper, we address the issue by imposing a new constraint on the design of high-rate SF-LDPC codes. We will compare the error rates of the constrained SF-LDPC codes and other optimized LDPC codes.

Original language	English
Title of host publication	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publication	Nano-Bio Circuit Fabrics and Systems
Pages	3781-3784
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2010.5537734
Publication status	Published - 31 Aug 2010
Event	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France Duration: 30 May 2010 → 2 Jun 2010

Conference

Conference	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Country/Territory	France
City	Paris
Period	30/05/10 → 2/06/10

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

More information

10.1109/ISCAS.2010.5537734

Cite this

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title = "Constructing high-rate scale-free LDPC codes",

abstract = "Low-density parity-check (LDPC) codes with scale-free (SF) symbol-node degree distribution have been shown to provide very good error performance. When the code rate becomes high, however, there will be a lot of degree-2 symbol nodes in the {"}pure{"} SF-LDPC codes. As a consequence, when the codes are constructed by connecting the symbol nodes with the check nodes, many small-size cycles will be formed. Such small-cycles will degrade the error performance of the codes. In this paper, we address the issue by imposing a new constraint on the design of high-rate SF-LDPC codes. We will compare the error rates of the constrained SF-LDPC codes and other optimized LDPC codes.",

author = "X. Zheng and Lau, \{Chung Ming\} and Tse, \{Chi Kong\}",

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doi = "10.1109/ISCAS.2010.5537734",

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Zheng, X, Lau, CM & Tse, CK 2010, Constructing high-rate scale-free LDPC codes. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537734, pp. 3781-3784, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 30/05/10. https://doi.org/10.1109/ISCAS.2010.5537734

Constructing high-rate scale-free LDPC codes. / Zheng, X.; Lau, Chung Ming; Tse, Chi Kong.
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 3781-3784 5537734.

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

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AU - Zheng, X.

AU - Lau, Chung Ming

AU - Tse, Chi Kong

PY - 2010/8/31

Y1 - 2010/8/31

N2 - Low-density parity-check (LDPC) codes with scale-free (SF) symbol-node degree distribution have been shown to provide very good error performance. When the code rate becomes high, however, there will be a lot of degree-2 symbol nodes in the "pure" SF-LDPC codes. As a consequence, when the codes are constructed by connecting the symbol nodes with the check nodes, many small-size cycles will be formed. Such small-cycles will degrade the error performance of the codes. In this paper, we address the issue by imposing a new constraint on the design of high-rate SF-LDPC codes. We will compare the error rates of the constrained SF-LDPC codes and other optimized LDPC codes.

AB - Low-density parity-check (LDPC) codes with scale-free (SF) symbol-node degree distribution have been shown to provide very good error performance. When the code rate becomes high, however, there will be a lot of degree-2 symbol nodes in the "pure" SF-LDPC codes. As a consequence, when the codes are constructed by connecting the symbol nodes with the check nodes, many small-size cycles will be formed. Such small-cycles will degrade the error performance of the codes. In this paper, we address the issue by imposing a new constraint on the design of high-rate SF-LDPC codes. We will compare the error rates of the constrained SF-LDPC codes and other optimized LDPC codes.

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DO - 10.1109/ISCAS.2010.5537734

M3 - Conference article published in proceeding or book

SN - 9781424453085

SP - 3781

EP - 3784

BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems

T2 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010

Y2 - 30 May 2010 through 2 June 2010

ER -

Constructing high-rate scale-free LDPC codes

Abstract

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ASJC Scopus subject areas

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