Compiler-assisted leakage-aware loop scheduling for embedded VLIW DSP processors

Meng Wang, Yi Wang, Duo Liu, Zhiwei Qin, Zili Shao

Research output: Journal article publicationJournal articleAcademic researchpeer-review

10 Citations (Scopus)


As feature size shrinks, leakage energy consumption has become an important concern. In this paper, we develop a compiler-assisted instruction-level scheduling technique to reduce leakage energy consumption for applications with loops on VLIW architecture. In the proposed technique, we obtain the schedule with minimum leakage energy from the ones that are generated by repeatedly regrouping a loop based on rotation scheduling and bipartite-matching. We conduct experiments on a set of benchmarks from DSPstone, Mediabench, Netbench, and MiBench based on the power model of the VLIW processors. The results show that our algorithm can achieve significant leakage energy saving compared with the previous work.
Original languageEnglish
Pages (from-to)772-785
Number of pages14
JournalJournal of Systems and Software
Issue number5
Publication statusPublished - 1 May 2010


  • DSP applications
  • Leakage power
  • Loop scheduling
  • VLIW architecture

ASJC Scopus subject areas

  • Software
  • Information Systems
  • Hardware and Architecture

Cite this