Code Size Reduction Technique and Implementation for Software-Pipelined DSP Applications

Qingfeng Zhuge, Bin Xiao, Edwin H.M. Sha

Research output: Journal article publicationJournal articleAcademic researchpeer-review

31 Citations (Scopus)


Software pipelining technique is extensively used to exploit instruction-level parallelism of loops, but also significantly expands the code size. For embedded systems with very limited on-chip memory resources, code size becomes one of the most important optimization concerns. This paper presents the theoretical foundation of code size reduction for software-pipelined loops based on retiming concept. We propose a general Code-size REDuction technique (CRED) for various kinds of processors. Our CRED algorithms integrate the code size reduction with software pipelining. The experimental results show the effectiveness of the CRED technique on both code size reduction and code size/performance trade-off space exploration.
Original languageEnglish
Pages (from-to)590-613
Number of pages24
JournalACM Transactions on Embedded Computing Systems
Issue number4
Publication statusPublished - 1 Nov 2003
Externally publishedYes


  • Algorithms
  • Design
  • DSP processors
  • Retiming
  • scheduling
  • software pipelining

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture


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