TY - PAT
T1 - Client-server architecture for multicore computer system to realize single-core-equivalent view
AU - Wang, Qixin
AU - Wang, Zhu
PY - 2020/5/5
Y1 - 2020/5/5
N2 - A client-server architecture is used in a multicore computer system to realize a single-core-equivalent (SCE) view. In the system, plural stacks, each having a core and a local cache subsystem coupled thereto, are divided into a client stack for running client threads, and server stacks each for running server threads. A shared cache having shared cache blocks, each coupled to the client stack and to one or more server stacks, is also used. The core of an individual server stack is configured such that computing resources utilizable in executing the server thread(s) are confined to the individual server stack and the shared cache block coupled thereto, isolating an inter-core interference caused by the server thread(s) to the client thread(s) to within the individual server stack, the shared cache block coupled thereto, any server stack coupled to this shared cache block, and the client stack to thereby realize the SCE view.
AB - A client-server architecture is used in a multicore computer system to realize a single-core-equivalent (SCE) view. In the system, plural stacks, each having a core and a local cache subsystem coupled thereto, are divided into a client stack for running client threads, and server stacks each for running server threads. A shared cache having shared cache blocks, each coupled to the client stack and to one or more server stacks, is also used. The core of an individual server stack is configured such that computing resources utilizable in executing the server thread(s) are confined to the individual server stack and the shared cache block coupled thereto, isolating an inter-core interference caused by the server thread(s) to the client thread(s) to within the individual server stack, the shared cache block coupled thereto, any server stack coupled to this shared cache block, and the client stack to thereby realize the SCE view.
UR - https://pdfpiw.uspto.gov/.piw?PageNum=0&docid=10642657&IDKey=19D21C78B4B1&HomeUrl=http%3A%2F%2Fpatft.uspto.gov%2Fnetacgi%2Fnph-Parser%3FSect1%3DPTO2%2526Sect2%3DHITOFF%2526p%3D1%2526u%3D%25252Fnetahtml%25252FPTO%25252Fsearch-bool.html%2526r%3D1%2526f%3DG%2526l%3D50%2526co1%3DAND%2526d%3DPTXT%2526s1%3DQixin.INNM.%2526s2%3Dmulticore.TI.%2526OS%3DIN%2FQixin%252BAND%252BTTL%2Fmulticore%2526RS%3DIN%2FQixin%252BAND%252BTTL%2Fmulticore
M3 - Patents granted
M1 - US10642657
Y2 - 2018/06/27
ER -