Abstract
With excellent current carrying capacity and extremely high thermal conductivity, carbon nanotube (CNT) has been proposed for interconnect and thermal interface material (TIM) applications. In this paper, we present a method of fabricating aligned CNT/copper composites on the silicon substrates and in the silicon dioxide vias. Electrical measurement of the CNT/copper composite vias demonstrates much lower electrical resistance than that of vias with CNT only. Thermal characterization shows the thermal resistance decreased by increasing copper loading into the CNT films. The electroplated copper fills the voids between the neighboring nanotubes. The improvement of the electrical and thermal conductance is resulted from the decreased porosity of the asgrown CNTs. The copper filling increases the contact area between the one-dimensional nanotube and the three-dimensional electrode or heat collector. This mechanically more robust material can sustain more rigorous electrical or thermal stressing cycling. Our results make CNT a step closer to the practical application of CNTs for the on-chip interconnections and thermal management.
Original language | English |
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Title of host publication | Proceedings - 57th Electronic Components and Technology Conference 2007, ECTC '07 |
Pages | 1224-1229 |
Number of pages | 6 |
DOIs | |
Publication status | Published - 22 Oct 2007 |
Externally published | Yes |
Event | 57th Electronic Components and Technology Conference 2007, ECTC '07 - Sparks, NV, United States Duration: 29 May 2007 → 1 Jun 2007 |
Conference
Conference | 57th Electronic Components and Technology Conference 2007, ECTC '07 |
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Country/Territory | United States |
City | Sparks, NV |
Period | 29/05/07 → 1/06/07 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering