Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection

H. S.Philip Wong; Subhasish Mitra; Deji Akinwande; Cara Beasley; Yang Chai; Hong Yu Chen; Xiangyu Chen; Gael Close; Jie Deng; Arash Hazeghi; Jiale Liang; Albert Lin; Luckshitha S. Liyanage; Jieying Luo; Jason Parker; Nishant Patil; Max Shulaker; Hai Wei; Lan Wei; Jie Zhang

doi:10.1109/IEDM.2011.6131594

Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection

H. S.Philip Wong
, Subhasish Mitra
, Deji Akinwande
, Cara Beasley
, Yang Chai
, Hong Yu Chen
, Xiangyu Chen
, Gael Close
, Jie Deng
, Arash Hazeghi
, Jiale Liang
, Albert Lin
, Luckshitha S. Liyanage
, Jieying Luo
, Jason Parker
, Nishant Patil
, Max Shulaker
, Hai Wei
, Lan Wei
, Jie Zhang

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

24 Citations (Scopus)

Abstract

Three key advances in device technology must be made to realize the potential of carbon nanotube transistors: (1) aligned CNT density of ≥200 CNT/μm on a wafer scale, (2) stable p- and n-type doping on the same wafer with control over the doping level, (3) low resistance metal to CNT contact at short (<20 nm) contact length. CNFET technology has now advanced to a point where large scale circuit level demonstration can be contemplated. This is made possible by advances in wafer-scale CNT growth, multiple CNT transfer, and imperfection-immune design techniques to overcome mis-positioned CNTs [11] and m-CNTs (e.g. VMR [18-19] and ACCNT [27]). In order to minimize CNT-specific variations (e.g. CNT count variations [45]), circuit design techniques co-optimized with process technology will play an important role. In the near future, CNFET circuit performance demonstration at GHz clock speed with the requisite device density is expected.

Original language	English
Title of host publication	2011 International Electron Devices Meeting, IEDM 2011
DOIs	https://doi.org/10.1109/IEDM.2011.6131594
Publication status	Published - 1 Dec 2011
Externally published	Yes
Event	2011 IEEE International Electron Devices Meeting, IEDM 2011 - Washington, DC, United States Duration: 5 Dec 2011 → 7 Dec 2011

Conference

Conference	2011 IEEE International Electron Devices Meeting, IEDM 2011
Country/Territory	United States
City	Washington, DC
Period	5/12/11 → 7/12/11

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

More information

10.1109/IEDM.2011.6131594

Cite this

Wong, H. S. P., Mitra, S., Akinwande, D., Beasley, C., Chai, Y., Chen, H. Y., Chen, X., Close, G., Deng, J., Hazeghi, A., Liang, J., Lin, A., Liyanage, L. S., Luo, J., Parker, J., Patil, N., Shulaker, M., Wei, H., Wei, L., & Zhang, J. (2011). Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection. In 2011 International Electron Devices Meeting, IEDM 2011 Article 6131594 https://doi.org/10.1109/IEDM.2011.6131594

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title = "Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection",

abstract = "Three key advances in device technology must be made to realize the potential of carbon nanotube transistors: (1) aligned CNT density of ≥200 CNT/μm on a wafer scale, (2) stable p- and n-type doping on the same wafer with control over the doping level, (3) low resistance metal to CNT contact at short (<20 nm) contact length. CNFET technology has now advanced to a point where large scale circuit level demonstration can be contemplated. This is made possible by advances in wafer-scale CNT growth, multiple CNT transfer, and imperfection-immune design techniques to overcome mis-positioned CNTs [11] and m-CNTs (e.g. VMR [18-19] and ACCNT [27]). In order to minimize CNT-specific variations (e.g. CNT count variations [45]), circuit design techniques co-optimized with process technology will play an important role. In the near future, CNFET circuit performance demonstration at GHz clock speed with the requisite device density is expected.",

author = "Wong, \{H. S.Philip\} and Subhasish Mitra and Deji Akinwande and Cara Beasley and Yang Chai and Chen, \{Hong Yu\} and Xiangyu Chen and Gael Close and Jie Deng and Arash Hazeghi and Jiale Liang and Albert Lin and Liyanage, \{Luckshitha S.\} and Jieying Luo and Jason Parker and Nishant Patil and Max Shulaker and Hai Wei and Lan Wei and Jie Zhang",

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day = "1",

doi = "10.1109/IEDM.2011.6131594",

language = "English",

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booktitle = "2011 International Electron Devices Meeting, IEDM 2011",

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Wong, HSP, Mitra, S, Akinwande, D, Beasley, C, Chai, Y, Chen, HY, Chen, X, Close, G, Deng, J, Hazeghi, A, Liang, J, Lin, A, Liyanage, LS, Luo, J, Parker, J, Patil, N, Shulaker, M, Wei, H, Wei, L & Zhang, J 2011, Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection. in 2011 International Electron Devices Meeting, IEDM 2011., 6131594, 2011 IEEE International Electron Devices Meeting, IEDM 2011, Washington, DC, United States, 5/12/11. https://doi.org/10.1109/IEDM.2011.6131594

Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection. / Wong, H. S.Philip; Mitra, Subhasish; Akinwande, Deji et al.
2011 International Electron Devices Meeting, IEDM 2011. 2011. 6131594.

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

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AU - Chen, Hong Yu

AU - Chen, Xiangyu

AU - Close, Gael

AU - Deng, Jie

AU - Hazeghi, Arash

AU - Liang, Jiale

AU - Lin, Albert

AU - Liyanage, Luckshitha S.

AU - Luo, Jieying

AU - Parker, Jason

AU - Patil, Nishant

AU - Shulaker, Max

AU - Wei, Hai

AU - Wei, Lan

AU - Zhang, Jie

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AB - Three key advances in device technology must be made to realize the potential of carbon nanotube transistors: (1) aligned CNT density of ≥200 CNT/μm on a wafer scale, (2) stable p- and n-type doping on the same wafer with control over the doping level, (3) low resistance metal to CNT contact at short (<20 nm) contact length. CNFET technology has now advanced to a point where large scale circuit level demonstration can be contemplated. This is made possible by advances in wafer-scale CNT growth, multiple CNT transfer, and imperfection-immune design techniques to overcome mis-positioned CNTs [11] and m-CNTs (e.g. VMR [18-19] and ACCNT [27]). In order to minimize CNT-specific variations (e.g. CNT count variations [45]), circuit design techniques co-optimized with process technology will play an important role. In the near future, CNFET circuit performance demonstration at GHz clock speed with the requisite device density is expected.

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DO - 10.1109/IEDM.2011.6131594

M3 - Conference article published in proceeding or book

SN - 9781457705052

BT - 2011 International Electron Devices Meeting, IEDM 2011

T2 - 2011 IEEE International Electron Devices Meeting, IEDM 2011

Y2 - 5 December 2011 through 7 December 2011

ER -

Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection

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ASJC Scopus subject areas

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