Three key advances in device technology must be made to realize the potential of carbon nanotube transistors: (1) aligned CNT density of ≥200 CNT/μm on a wafer scale, (2) stable p- and n-type doping on the same wafer with control over the doping level, (3) low resistance metal to CNT contact at short (<20 nm) contact length. CNFET technology has now advanced to a point where large scale circuit level demonstration can be contemplated. This is made possible by advances in wafer-scale CNT growth, multiple CNT transfer, and imperfection-immune design techniques to overcome mis-positioned CNTs  and m-CNTs (e.g. VMR [18-19] and ACCNT ). In order to minimize CNT-specific variations (e.g. CNT count variations ), circuit design techniques co-optimized with process technology will play an important role. In the near future, CNFET circuit performance demonstration at GHz clock speed with the requisite device density is expected.
|Conference||2011 IEEE International Electron Devices Meeting, IEDM 2011|
|Period||5/12/11 → 7/12/11|
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry