Analytical solutions for interconnect stress in board level drop impact

E. H. Wong; Y. W. Mai; S. K.W. Seah; K. M. Lim; T. B. Lim

doi:10.1109/ECTC.2006.1645905

Analytical solutions for interconnect stress in board level drop impact

E. H. Wong, Y. W. Mai, S. K.W. Seah, K. M. Lim, T. B. Lim

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

12 Citations (Scopus)

Abstract

Closed form analytical solutions for the stresses in the IC package-to-PCB interconnection when subjected to JEDEC STD board level drop test have been developed and validated. The solutions offer useful insights into the mechanics of board level interconnection in drop impact and have been used to (i) investigate the degrees of symmetry of PCB flexing on the interconnection stress; (ii) perform parametric design analysis; and (iii) establish an equivalent board for JEDEC drop test.

Original language	English
Title of host publication	Proceedings - IEEE 56th Electronic Components and Technology Conference
Pages	1808-1815
Number of pages	8
DOIs	https://doi.org/10.1109/ECTC.2006.1645905
Publication status	Published - 2006
Externally published	Yes
Event	IEEE 56th Electronic Components and Technology Conference - San Diego, CA, United States Duration: 30 May 2006 → 2 Jun 2006

Publication series

Name	Proceedings - Electronic Components and Technology Conference
Volume	2006
ISSN (Print)	0569-5503

Conference

Conference	IEEE 56th Electronic Components and Technology Conference
Country/Territory	United States
City	San Diego, CA
Period	30/05/06 → 2/06/06

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

More information

10.1109/ECTC.2006.1645905

Cite this

Wong, E. H., Mai, Y. W., Seah, S. K. W., Lim, K. M., & Lim, T. B. (2006). Analytical solutions for interconnect stress in board level drop impact. In Proceedings - IEEE 56th Electronic Components and Technology Conference (pp. 1808-1815). Article 1645905 (Proceedings - Electronic Components and Technology Conference; Vol. 2006). https://doi.org/10.1109/ECTC.2006.1645905

@inproceedings{ed169e9e96184ade9f4f512d93e7336f,

title = "Analytical solutions for interconnect stress in board level drop impact",

abstract = "Closed form analytical solutions for the stresses in the IC package-to-PCB interconnection when subjected to JEDEC STD board level drop test have been developed and validated. The solutions offer useful insights into the mechanics of board level interconnection in drop impact and have been used to (i) investigate the degrees of symmetry of PCB flexing on the interconnection stress; (ii) perform parametric design analysis; and (iii) establish an equivalent board for JEDEC drop test.",

author = "Wong, {E. H.} and Mai, {Y. W.} and Seah, {S. K.W.} and Lim, {K. M.} and Lim, {T. B.}",

year = "2006",

doi = "10.1109/ECTC.2006.1645905",

language = "English",

isbn = "1424401526",

series = "Proceedings - Electronic Components and Technology Conference",

pages = "1808--1815",

booktitle = "Proceedings - IEEE 56th Electronic Components and Technology Conference",

note = "IEEE 56th Electronic Components and Technology Conference ; Conference date: 30-05-2006 Through 02-06-2006",

}

Wong, EH, Mai, YW, Seah, SKW, Lim, KM & Lim, TB 2006, Analytical solutions for interconnect stress in board level drop impact. in Proceedings - IEEE 56th Electronic Components and Technology Conference., 1645905, Proceedings - Electronic Components and Technology Conference, vol. 2006, pp. 1808-1815, IEEE 56th Electronic Components and Technology Conference, San Diego, CA, United States, 30/05/06. https://doi.org/10.1109/ECTC.2006.1645905

Analytical solutions for interconnect stress in board level drop impact. / Wong, E. H.; Mai, Y. W.; Seah, S. K.W. et al.
Proceedings - IEEE 56th Electronic Components and Technology Conference. 2006. p. 1808-1815 1645905 (Proceedings - Electronic Components and Technology Conference; Vol. 2006).

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

TY - GEN

T1 - Analytical solutions for interconnect stress in board level drop impact

AU - Wong, E. H.

AU - Mai, Y. W.

AU - Seah, S. K.W.

AU - Lim, K. M.

AU - Lim, T. B.

PY - 2006

Y1 - 2006

N2 - Closed form analytical solutions for the stresses in the IC package-to-PCB interconnection when subjected to JEDEC STD board level drop test have been developed and validated. The solutions offer useful insights into the mechanics of board level interconnection in drop impact and have been used to (i) investigate the degrees of symmetry of PCB flexing on the interconnection stress; (ii) perform parametric design analysis; and (iii) establish an equivalent board for JEDEC drop test.

AB - Closed form analytical solutions for the stresses in the IC package-to-PCB interconnection when subjected to JEDEC STD board level drop test have been developed and validated. The solutions offer useful insights into the mechanics of board level interconnection in drop impact and have been used to (i) investigate the degrees of symmetry of PCB flexing on the interconnection stress; (ii) perform parametric design analysis; and (iii) establish an equivalent board for JEDEC drop test.

UR - http://www.scopus.com/inward/record.url?scp=33845565188&partnerID=8YFLogxK

U2 - 10.1109/ECTC.2006.1645905

DO - 10.1109/ECTC.2006.1645905

M3 - Conference article published in proceeding or book

AN - SCOPUS:33845565188

SN - 1424401526

SN - 9781424401529

T3 - Proceedings - Electronic Components and Technology Conference

SP - 1808

EP - 1815

BT - Proceedings - IEEE 56th Electronic Components and Technology Conference

T2 - IEEE 56th Electronic Components and Technology Conference

Y2 - 30 May 2006 through 2 June 2006

ER -

Analytical solutions for interconnect stress in board level drop impact

Abstract

Publication series

Conference

ASJC Scopus subject areas

More information

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