Abstract
NAND flash memory is widely used in embedded systems due to its non-volatility, shock resistance and high cell density. In recent years, various Flash Translation Layer (FTL) schemes (especially hybrid-level FTL schemes) have been proposed. Although these FTL schemes provide good solutions in terms of endurance and wear-leveling, none of them have considered to reuse free pages in both data blocks and log blocks during a merge operation. By reusing these free pages, less free blocks are needed and the endurance of NAND flash memory is enhanced. We evaluate our reuse strategy using a variety of application specific I/O traces from Windows systems. Experimental results show that the proposed scheme can effectively reduce the erase counts and enhance the endurance of flash memory.
| Original language | English |
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| Title of host publication | Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011 |
| Pages | 14-19 |
| Number of pages | 6 |
| Publication status | Published - 31 May 2011 |
| Event | 14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011 - Grenoble, France Duration: 14 Mar 2011 → 18 Mar 2011 |
Conference
| Conference | 14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011 |
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| Country/Territory | France |
| City | Grenoble |
| Period | 14/03/11 → 18/03/11 |
ASJC Scopus subject areas
- General Engineering