In this paper we present an efficient structural approach for diagnosing board interconnects using boundary-scan. Whereas existing diagnosis approaches assume only wired-AND or wired-OR bridging fault model, we consider a more complex bridging short fault model in a CMOS circuit environment. The diagnostic test set is generated on the basis of graph theoretic technique and the adjacency fault model is adopted. By using the structural information of the wiring layout, the test length can be reduced. Both one-step and two-step diagnosis algorithms are given. They guarantee the complete diagnosis of multiple interconnect faults with no aliasing or confounding. The algorithms have been evaluated by simulation on several benchmark layouts and randomly generated layouts. Simulation results show that more than 50% reduction in the number of tests can be achieved for two-step diagnosis when the fault rate is very small, such as in a matured product line. This can significantly save the diagnosis cost for boundary-scan testing.
ASJC Scopus subject areas
- Electrical and Electronic Engineering