Abstract
Scratch-pad memory (SPM) is widely used in embedded systems. It is a topical and crucial subject to reduce power consumption for SPM systems, since high power consumption can reduce systems reliability and increase the cost and size of heat sinks. In this paper, we propose an effective approach of power reducing to scale down voltage and frequency as much as possible. We first pipelined data transference and processing. Second, we find the comparative time slack between fast data processing and low data transference, and then provide both single and dynamic scaling to reduce power consumption. We conduct our approach on the simulator of Trimaran, and the experimental results show that the approach achieves significant power reduction improvement while the run-time performance outperforms previous work.
Original language | English |
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Title of host publication | Proceedings - 2011 International Conference on Parallel Processing Workshops, ICPPW 2011 |
Pages | 229-237 |
Number of pages | 9 |
DOIs | |
Publication status | Published - 7 Nov 2011 |
Event | 2011 International Conference on Parallel Processing Workshops, ICPPW 2011 - Taipei City, Taiwan Duration: 13 Sept 2011 → 16 Sept 2011 |
Conference
Conference | 2011 International Conference on Parallel Processing Workshops, ICPPW 2011 |
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Country/Territory | Taiwan |
City | Taipei City |
Period | 13/09/11 → 16/09/11 |
Keywords
- DVFS
- Embedded system
- Power
- Scratch-pad memory
ASJC Scopus subject areas
- Software
- General Mathematics
- Hardware and Architecture